2.0 V Bipolar/CMOS differential logic methodology for iterative network implementation

Abstract

A Bipolar/CMOS differential logic methodology for iterative network implementation is presented. Low voltage swing on internal connections allows for a very fast signal propagation through the time critical path of the network. A delay time of 134 ps/bis was found for a differential network tree with three levels of stacked transistors. A supply voltage reduction to 2.0 V was obtained using MOS transistors for external variable path. A proper operation of the network is assured at temperatures up to 150°C.