Abstract
The biggest hurdle in today’s processors is heat dissipation. Complementary Metal Oxide Semiconductor (CMOS) is used currently. In CMOS, irreversible computational occurs which leads to heat and energy dissipation. One of the solutions is to use reversible logic. In this paper, a single-bit comparator design is proposed. The device-level implementation of a reversible comparator using Quantum dot Cellular Automata (QCA) is proposed. The design is made using reversible Fredkin and Feynman gates. These are implemented using QCA. Further, the 1-bit magnitude comparator comprised of Feynman and Fredkin gates is designed. In this paper, the device-level reversible logic implementation and energy calculations are claimed although the performance parameters are not that optimized.
Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
