16‐qam carrier recovery with selective gated phase‐locked loop

Abstract

AbstractIt is important for the 16QAM carrier recovery circuit to have low phase jitter as well as only four stable phase points. In this paper, a novel carrier recovery with selective gated phase‐locked loop (PLL) is proposed which uses only the error information of the 4PSK signal and an identical phase signal; its construction and noise characteristics are also described. First, a concrete construction based on a working priciple and digitalized circuitry is given. Next, the phase jitter due to additive white Gaussian noise in a carrier tracking loop with binary phase comparator (PC) characteristic is analyzed using an equivalent linearization technique; also, it is shown that the carrier recovery loop can be described in a linear model of the past by introducing equivalent linear gain, equivalent input noise and the degradation factor caused by the symbol error. From this study, we conclude that with the selective gated PLL, the phase jitter performance of the carrier recovery can be improved by about 6 dB over that of the carrier recovery without the selective gated PLL. This has enabled us to improve the phase noise, power density, locking characteristic, tracking characteristic, etc., by about 100%. The noise characteristics are almost the same as that of 4PSK carrier recovery. The numerical calculations have been done for the equivalent PC. This recovery system does not have false lock points.