155 GHz FMCW and Stepped-Frequency Carrier OFDM Radar Sensor Transceiver IC Featuring a PLL With <30 ns Settling Time and 40 fs rms Jitter

Abstract

A radar transceiver with two transmitters (TXs) and two receivers (RXs) is reported in 22 nm fully depleted silicon-on-insulator (FDSOI) CMOS. It includes a novel 200 MHz bandwidth 80 GHz phase-locked loop (PLL) based on a single-sideband (SSB) upconverter and an 11 GHz bandwidth phase-frequency detector to achieve >8 GHz locking range with record phase noise of −97, −103, and −113 dBc/Hz at 100 kHz, 1 MHz, and 10 MHz offset, respectively, and rms jitter < 40 fs. Stepped-frequency chirps with orthogonal frequency-division multiplexing (OFDM) modulation covering the 152–160 GHz range were demonstrated in a through-the-air loopback link along with a record settling time < 30 ns, limited by the test equipment. The RXs have an IIP3 of −8 dBm, SSB noise figure between 7.5 and 10 dB and a conversion gain of 15 dB, controllable from the LNA back gate over a range of 12 dB. The OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1 dB</sub> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {SAT}}$ </tex-math></inline-formula> of the power amplifier (PA) in each TX are 5 and 9 dBm, respectively. The IQ amplitude mismatch and phase error of each RX are < 0.5 dB and 1°, respectively, while the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathbf {out}}$ </tex-math></inline-formula> mismatch between the TXs is < 1 dB. The sensor consumes 1.13 W, with 300 mW by the PLL, 275 mW by the 160 GHz local oscillator (LO)-tree, 190 mW by each TX, and 87.5 mW by each RX.