14-bit 100 MS/s 121 mW pipelined ADC**Project supported by the National Key Technology R&D Program (No. 2012BAI13B07).

Abstract

This paper presents a high-speed high-resolution pipelined ADC with low power and small area. The proposed ADC is designed based on the analysis of the stage scaling theory and the residual amplifiers are shared by two cascading MDACs to reduce power consumption. Shared op-amps with two split input paths are presented in this paper to eliminate the nonlinearity effects such as memory effect and crosstalk. Dynamic pre-amplified comparators are employed to decrease the static power consumption and suppress the kick-back in the comparators. This ADC is implemented in SMIC 0.18 μm CMOS process with an area of 3.1 mm2. With a sampling rate of 100 MS/s, spurious-free dynamic range (SFDR) and signal-to-noise plus distortion ratio (SNDR) of the ADC are 82.7 dB and 69.1 dB, respectively. For signals up to 100 MHz, the SFDR and SNDR achieve 81.4 dB and 65.8 dB. The power consumption is 121 mW with a 1.8 V supply voltage.