Abstract
A -3.3-V half-rate clock 4:1 multiplexer implemented in a 210-GHz f/sub T/ 0.13-/spl mu/m SiGe-bipolar technology and operating up to 132 Gb/s is reported. Among many design challenges, the control of on-chop clock distribution was critical to achieve such a high data rate. At 100 Gb/s, the chip operates reliably down to -3.0-V supply voltage and up to 100/spl deg/C chip temperature. The circuit consumes 1.45 W from a -3.3-V supply voltage and exhibits less than 340-fs RMS jitter on the output data.
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