13.2: Equalizer and Clock/Data Recovery Circuits in SDICs for Intra‐Panel Interface

Abstract

This work presents a front‐end circuits including of the equalizer and clock/data recovery (CDR) circuits in the source driver ICs (SDICs) for the TFT‐LCD intra‐panel interfaces. For 4K2K LCD TV, the data rate of SDICs has been increased to 5Gbps per lane, so it is a challenge to develop the front‐end circuits when they suffered from the serious ISI and large jitters in received data. In the front‐end circuits meeting the BOE’s CHPI specification, a cascade equalizer are used to widen the eye diagram to reduce BER and a dual loop CDR circuits are used to tolerate the large input jitter and power noise.