1.23-pJ/bit 25-Gb/s Inductor-Less Optical Receiver With Low-Voltage Silicon Photodetector

Abstract

This paper presents the design and measurement results of an inductor-less and power-efficient 25-Gb/s optical receiver in 65-nm TSMC technology. Furthermore, the design and characteristics of a novel 850-nm low-voltage silicon-on-insulator-based all-silicon photodetector (Si-PD) are demonstrated. The proposed receiver front end consists of an inverter-based feedback transimpedance amplifier and three stages of inverter-based Cherry–Hooper post-amplifier. To this structure, local positive feedback and third-order interleaved active feedback are added to increase the bandwidth of the front end. Measurement results show that the receiver front end has a transimpedance gain of $69.4~\text {dB}\Omega $ , a bandwidth of 13.6 GHz, and an input-referred current noise of 3.28 $\mu \text {A}_{\text {rms}}$ . It occupies only 0.0056 mm2 and consumes 30.8 mW at 1.1-V supply voltage. The proposed Si-PD has a responsivity of 0.05 A/W (at 850 nm), a dark current of 0.02 nA, and a bandwidth of 12.6 GHz at 0-V bias voltage. For a bit error rate of 10−12, the optical receiver with a wire-bonded Si-PD has a sensitivity of 46 and 54 $\mu \text {A}_{p-p}$ at data rates of 20 and 25 Gb/s, respectively, at a reverse-bias voltage of 0.41 V. The energy efficiency of the all-silicon 850-nm optical receiver is 1.23 pJ/bit at 25-Gb/s data rate. The receiver front end was also measured with an electrical input signal with supply voltages lower than 1.1 V. For an input sensitivity of $5~\text {mV}_{p-p}$ , the receiver front end has energy efficiencies of 0.425 and 0.8 pJ/bit at data rates of 20 and 25 Gb/s, for supply voltages of 0.85 and 1 V, respectively.