12.5-Gb/s Full-Rate CDR With Wideband Quadrature Phase Shifting in Data Path

Abstract

A 12.5-Gb/s full-rate clock and data recovery (CDR) circuit that utilizes an open-loop quadrature clock generator for wideband 90 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> phase shifting in the data path is presented. The differential clock from a voltage-controlled oscillator (VCO) is split into quadrature phases and subsequently mixed with data to provide in-phase and quadrature components of the data over a broad range of frequencies in the vicinity of the nominal data rate. The quadrature data phases are employed for the detection of clock phase misalignment in a mixer-based phase detector. A proof-of-concept prototype chip that integrates the critical building blocks of the proposed CDR is fabricated in a 90-nm CMOS technology. The CDR achieves a bit error rate of <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> in response to 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> - 1 pseudorandom-binary-sequence data, while the chip (which excludes VCO) consumes 84 mW from a 1.2-V supply.