11-ps resolution time interval counter in CMOS ASIC

Abstract

This paper describes a design and test results of time interval counter (TIC), which provides a high resolution of 10.7 ps within a wide measurement range of 1 ms. To achieve these parameters the counting method with a two-stage interpolation within a single clock period is involved. A sub-gate delay resolution is obtained with the aid of the differential delay line technique. To diminish the nonlinearities of conversion and finally to improve the precision of measurement a novel matrix of differential delay lines is proposed. The TIC is implemented as an Application Specific Integrated Circuit (ASIC) in 0.35 μm CMOS process.