10GHz Low Current Mismatch Pseudo-Differential Charge Pump Phase-Locked Loop Circuit Design

Abstract

Design a 10GHz low current mismatch, low jitter fast locking charge pump phase-locked loop based on UMC 28nm HLP CMOS process. This design reduces the charge pump current mismatch by using a negative feedback loop method; the voltage-controlled oscillator uses a pseudo-differential structure to improve the frequency tuning range and proposes a low voltage high matching current mirror applied to the tail current switching control array to improve the robustness of the voltage controlled oscillator in a low voltage environment and reduce the phase noise of the voltage-controlled oscillator. The simulation results show that: the charge pump charge/discharge current mismatch is less than 2%; the voltage-controlled oscillator frequency tuning range is from 9.6 to 10. 4GHz, and the phase noise is -86.7dBc/Hz at the output frequency of 1MHz; the phase-locked loop lock time is 0. 75us, and the jitter is 2ps.