10Gb/s inverter based cascode transimpedance amplifier in 40nm CMOS technology

Abstract

This work presents the design and performance of a 10Gbit/s transimpedance amplifier (TIA) implemented in a 40nm CMOS technology. The introduced TIA uses an inverter based cascode feedback (Inv-Cascode-TIA) with shunt feedback resistor. The TIA is followed by an one-stage single-ended common-source amplifier (CS), a two-stage differential amplifier and a 50Ω differential output driver to provide an interface to the measurement setup. The optical receiver shows an optical sensitivity of -21.4dBm for a BER= 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> . The transimpedance amplifier achieves a transimpedance gain of 55.3dBΩ, 8GHz bandwidth with 0.45pF total input capacitance. The power consumption of the TIA is 3.01mW and the complete chip dissipates 19.25mW for a 1.2V single supply voltage. The complete optical receiver has a 69.2dBΩ transimpedance gain and 7GHz bandwidth.