10Gb/s RS-BCH Concatenated Encoder with Pipelined Strategies for Fiber Communication

Abstract

This paper presents a 10Gb/s concatenated encoder compatible with the protocol of G.975. To achieve the high data rate, 8 RS encoders work based on the pipelined pattern. After the interleaving realized with 8 RAM blocks, the output of RS encoders are sent to 64 BCH encoders which work parallel. This concatenated encoder has been implemented in Xilinx Vertex5 FPGA, and the measurement results show that the data rate of 10Gb/b can be realized under the working frequency of 156MHz. About 9711 registers, 6984 LUTs and 40 Block-RAMs are utilized for the whole encoder.