Abstract
Advanced CMOS devices below 28nm allow supply voltages lower than 1V. For applications with higher input voltage in such devices, stacked MOSFET structures with a three-level technology are commonly employed. The stacked structure can also reduce the output voltage ripple substantially. Figure 10.5.1 shows a three-level single-inductor triple-output (SITO) converter and also compares the transient response with the SITO converter without the three-level technique. The three-level topology applies three different voltages, V in , 1/2V in , and V SS , to the node V X . The operation mode is determined by the duty cycle, i.e., the node V x swings between 1/2V in and V SS when duty cycle (D in and V in , otherwise (D>0.5). In state-of-the-art [1–3], the key issue of the three-level topology is how to balance the cross voltage of flying capacitor C FLY at the point of 1/2V in . In general, the restrained output voltage ripple and the flatter inductor current (I L ) slope seriously result in worse transient response and severe cross-regulation (CR) problems, respectively. Results in Figure 10.5.1 show that the three-level SITO converter achieves a smaller output voltage ripple in steady state, but it causes the problems of slower transient response time, longer recovery time, larger overshoot/undershoot, and severe CR. Thus, it is desired to develop a technique that can adjust the cross voltage of C FLY such that the three-level topology achieves higher efficiency, lower output voltage ripple, and fast transient response simultaneously.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have