10.5 A digital PLL with feedforward multi-tone spur cancelation loop achieving −73dBc fractional spur and −110dBc Reference Spur in 65nm CMOS

Abstract

A low-spur PLL is desirable for many applications since it avoides mixing unwanted blocker signals, prevents emission mask violations or minimizes jitter in the clock source. Internal spurs result from the nature of PLL operation and include reference spurs and fractional spurs when the PLL is operated in fractional-N mode. External spurs are caused by nearby disturbances, such as coupling from other clock domains in an SoC design. To achieve ultra-low spur levels, this work proposes a feedforward multi-tone spur cancellation loop for a fractional-N digital PLL architecture. The proposed scheme aims to cancel: a) fractional spurs caused by finite time-to-digital converter (TDC) quantization steps and its DNL when operated in fractional-N mode; b) external spurious tones that are in a harmonic relationship, and c) independent series of spurious tones that are not in a mutually harmonic relationship by cascading cancellation loops. A proof-of-concept 3-to-5GHz digital PLL prototype is implemented in 65nm CMOS and achieves a worst-case reference spur of −110.1dB and a worst-case in-band fractional spur of −73.66dB, both of which are lower than the reported spur level among state-of-the-art PLLs [1–4]. The internal or external spur magnitude reduction after enabling the cancellation loop ranges from 15 to 50dB over different operation scenarios; this reduction validates the effectiveness of the proposed spur cancellation scheme.