100 MHz Random Number Generator Design Using Interleaved Metastable NAND/NOR Latches

Abstract

This investigation demonstrates a wide bandwidth random number generator (RNG) based on interleaved NAND-/NOR-based SR (set-reset) latches. More specifically, the metastability of SR latches driven by the same input causing undefined output states is exploited. To achieve higher irregular sampling of the SR latches, not only NAND-based SR latches and NOR-based SR latches are interleaved integrated, their inputs are also randomly selected by another array of metastable SR latches. Namely, a 2-layer RNG architecture is realized to avoid locking phenomenon and enhance randomness. The proposed 2-layer RNG is realized using typical 40-nm CMOS process. All-PTV-corner (process, temperature, voltage) post-layout simulations validate that the proposed RNG passes long run test and mono-bit test given 100 MHz clock rate.