Abstract
We present a new data acquisition system under development for the next upgrade of the LHCb experiment at CERN. We focus in particular on the design of a new generation of readout boards, the PCIe40, and on the viability of PCI-Express as an interconnect technology for high speed readout. We show throughput measurements across the PCI-Express bus, on Altera Stratix 5 devices, using a DMA mechanism and different synchronization schemes between the FPGA and the readout unit. Finally we discuss hardware and software design considerations necessary to achieve a data throughput of 100 Gbps in the final readout board.
Highlights
24 inputs in nominal DAQ configuration Up to 48 inputs for low occupancy sub-detectors Up to 48 bidirectional links for SOL40 configuration
PCIe switch tested on GPGPU but not yet on FPGA
FPGA buffer is divided in DMA sections
Summary
24 inputs in nominal DAQ configuration Up to 48 inputs for low occupancy sub-detectors Up to 48 bidirectional links for SOL40 configuration. Altera PCIe IP only implements Gen3 x8 Use two and bond them with a PCIe switch nVIDIA does it with their dual GPGPUs, and it works! Sustained 112.8 Gbps observed downstream from switch GBT optical readout link Streaming source/sink Memory-mapped master/slave PCIe MPS is 256B, no advantage in overloading DMA engine Matches MMU page size in event builder address space
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