100 Gbit/s AES-GCM Cryptography Engine for Optical Transport Network Systems: Architecture, Design and 40 nm Silicon Prototyping

Abstract

This work reports the architecture, design, verification and prototyping of a 100 Gbit/s AES-GCM cryptography engine specifically conceived for securing optical transport network (OTN) systems. The proposed solution addresses the main systemic issues related to the use of a block cipher in an OTN system, such as the need for data packetization, the transport of cryptographic auxiliary information, the hitless cipher key change mechanism, and others. The implemented functional logic block (IP core) interfaces with other OTN processing blocks with a 640-bit data path running at 180 MHz. The design was successfully verified by simulations based on regular test benches and the encryption algorithm was validated against standardized test vectors. The full engine was integrated into an 8-million gate 40 nm OTN Processor ASSP developed by CPQD for the Brazilian telecom industry. Chip and ASSP design metrics are also presented. The overall concept and design ideas can contribute to other works related to both OTN and cryptography technology.