Abstract
This paper presents a new approach based on the use of a Current Steering (CS) technique for the design of fully integrated Gm–C Low Pass Filters (LPF) with sub-Hz to kHz tunable cut-off frequencies and an enhanced power-area-dynamic range trade-off. The proposed approach has been experimentally validated by two different first-order single-ended LPFs designed in a 0.18 µm CMOS technology powered by a 1.0 V single supply: a folded-OTA based LPF and a mirrored-OTA based LPF. The first one exhibits a constant power consumption of 180 nW at 100 nA bias current with an active area of 0.00135 mm2 and a tunable cutoff frequency that spans over 4 orders of magnitude (~100 mHz–152 Hz @ CL = 50 pF) preserving dynamic figures greater than 78 dB. The second one exhibits a power consumption of 1.75 µW at 500 nA with an active area of 0.0137 mm2 and a tunable cutoff frequency that spans over 5 orders of magnitude (~80 mHz–~1.2 kHz @ CL = 50 pF) preserving a dynamic range greater than 73 dB. Compared with previously reported filters, this proposal is a competitive solution while satisfying the low-voltage low-power on-chip constraints, becoming a preferable choice for general-purpose reconfigurable front-end sensor interfaces.
Highlights
The achievement of low form factor system-on-chip (SoC) sensing devices with extended battery life or even battery-less systems capable of measuring a great variety of parameters makes the design of every single block within a general-purpose front-end sensor interface a challenge
A front-end sensor interface (Figure 1a) typically includes a transducer to convert the parameter to be measured into an electrical signal; a preconditioning stage consisting of a low-noise preamplifier (LNP) amplifies the signal and the low-pass filtering stage (LPF) takes out the out-of-band interferences and noise; the digitalization stage (ADC) allows further signal processing by a μC to extract the desired signal information [1,2,3,4]
CMOS topology in terms of power and area, still remains a challenge in analog circuit design, demanding new techniques and strategies to meet simultaneously all these required performances into a SoC. The design of such a LP filter is the motivation of this work, with the targeted design specifications: tunable cutoff frequency covering the main signal ranges of Table 1, power consumption below the ~μW; area below ~0.1 mm2 ; bias currents greater than ~10–100 nA to be reliably generated on-chip and a dynamic range above 60 dB
Summary
The achievement of low form factor system-on-chip (SoC) sensing devices with extended battery life or even battery-less systems capable of measuring a great variety of parameters makes the design of every single block within a general-purpose front-end sensor interface a challenge. CMOS topology in terms of power and area, still remains a challenge in analog circuit design, demanding new techniques and strategies to meet simultaneously all these required performances into a SoC The design of such a LP filter is the motivation of this work, with the targeted design specifications: tunable cutoff frequency covering the main signal ranges of Table 1, power consumption below the ~μW; area below ~0.1 mm ; bias currents greater than ~10–100 nA to be reliably generated on-chip and a dynamic range above 60 dB. 1.0 V-0.18 μm designed LPF using a folded-cascode core OTA to achieve an ultra-efficient power and area architecture Both approaches exhibit wide tunable cutoff frequencies (~80 mHz–~1.2 kHz Mirrored, ~100 mHz–152 Hz Folded), low power (1.75 μW@Ibias = 500 nA-Mirrored and 180 nW, @Ibias = 100 nA-Folded), and reduced size (0.0137 mm2 -Mirrored and 0.0135 mm2 -Folded), while keeping a high dynamic range (>73 dB-Mirrored and >78 dB-Folded), enhancing the state-of-the-art power-area-DR tradeoff.
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