10 - Case Study: A Bit-Vector Arithmetic Package

Abstract

This chapter describes a case study in which a package of procedures and functions to perform arithmetic operations on bit-vectors is developed. The subprograms treat the bit- vectors as binary-encoded integers. VHDL does not provide arithmetic operations for bit- vectors. There are several alternative encoding schemes, which can be used to represent numbers, each with different interpretations of the bits within a vector. VHDL leaves the choice of representation to the designer. The study provides for both unsigned integers and signed integers using two's-complement representations. The first group of operations that is provided by the package is a number of conversions functions that convert between numeric and bit-vector values. Second, the package includes several forms of addition, subtraction, multiplication, and division operations. The third group of operations included in the package is relational functions for comparing two signed binary vectors. The final group of operations in the package is the extension functions.