1 V SOI NMOSFET with suppressed floating body effects

Abstract

A partially depleted CMOS compatible SOI NMOSFET structure with suppressed floating body effects is proposed in this paper. The structure uses high dose Si implantation to reduce the carrier lifetime in the floating body region near the bottom channel/buried oxide interface and convert that region into an amorphous–polycrystalline one. The fabricated devices exhibit suppressed floating body effects without area penalty or other adverse effects. Characterization results show that the fabricated devices are suitable for low power 1 V applications.