1 /spl mu/m MOSFET VLSI technology. III. Logic circuit design methodology and applications

Abstract

For pt. II see ibid., vol.SC14, no.2, p.247 (1979). Logic circuits were designed and fabricated in a 1 /spl mu/m silicon-gate MOSFET technology. First, conventional random logic chip images using the largely one-dimensional `Weinberger' layout are examined. The image is able to provide chips with an average circuit delay of 3 ns at the 8000 circuit level of integration. Second, two forms of PLA and PLA-based macros are discussed. A dynamic PLA, used in a microprocessor cross section and including 105 product terms, which achieves a 56 ns cycle time is described. A static PLA, designed for 21-ns delay and achieving measured delays from 13 to 21 ns, is also described. Extensions, particularly into low-temperature operation, are discussed.