1.25 /spl mu/m Deep-Groove-Isolated Self-Aligned Bipolar Circuits

Abstract

This paper concerns the design and characteristics of the high-performance bipolar switching devices and circuits for digital applications at lithographic dimensions of about 1 /spl mu/m. The impurity profile of the transistors is optimized for speed while maintaining sufficient current gain and punchthrough voltage. The circuits were fabricated on epitaxial wafers of a 0.5 /spl mu/m flat zone in an advanced bipolar technology featuring self-aligned polysilicon base and emitter contacts, deep-groove device isolation, and electron beam lithography. The experimental results show that n-p-n transistors exhibit a current gain greater than 40 at current densities as high as 1.3 mA//spl mu/m/sup 2/. As a result of reduced line width and polysilicon contacts, the current gain of Iateral epi-base p-n-p transistors is greater than 20 at low-current levels and remains greater than 1 at a current density as high as 0.12 mA//spl mu/m emitter edge. ECL (FI = FO = 1) circuits show a gate delay as low as 114 pS at a power dissipation of 4.9 mW. High-density I/sup 2/L/MTL circuits (average FI = 2, FO = 2.5, C/sub w/ = 90 fF) show delay of 0.91 ns at 0.17 mW. These results demonstrate that the present bipolar technology provides not only high-speed circuits, but also circuits for VLSI applications with density comparable to MOSFET.