1.2 V full-swing BiDPL logic gate

Abstract

A novel full-swing BiDPL gate is proposed with greatly reduced power consumption, improved power efficiency at supply voltages down to 1.2 V and significantly reduced layout area. The new logic gate behaves like a standard CMOS for low fanout and is more power efficient for high fanout. The new circuit was compared to bootstrapped bipolar, bootstrapped full-swing and Seng-Rofail's bootstrapped BiCMOS logic styles, and the standard CMOS logic style. Low-power methodology was used for the optimization of all gates. Tests were performed at various power supply voltages (0.9–3 V), with various output load capacitances (0.1–1 pF), at a frequency of 50 MHz and temperature 27°C. At 1.2 V and output loads 0.1–0.7 pF the new circuit has up to 2.9 times better power efficiency than the best bootstrapped BiCMOS style reported and uses between 16 and 32% less switching power. Under optimal conditions ( V dd = 1.6 V), the new design has up to 18% higher power efficiency than conventional CMOS logic for loads 0.55–1 pF and up to 117% better power efficiency than the best reported BiCMOS style for output loads 0.1–0.68 pF. Test circuits have been designed and fabricated with 0.8 μm BiCMOS technology with V thn = 0.8 V and V thp = − 0.9 V.