Abstract
In this paper, we propose a new architecture for Capacitance-to-Digital convertor. We clarified the configuration that utilizes the time resolution of the frequency-Locked-Loop oscillator using a switched capacitor that enables stable operation, and integrated the circuit using 0.18µm standard CMOS technology. As a result, a power supply voltage of 1.2V, a capacitance resolution of 15aF, ENOB of 15.8bit, high resolution, and wide dynamic range conversion characteristics were achieved.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
