1+1 <2: Efficient Automatic Standard Cell Sharing Between Digital VLSI Designs for Area Saving

Abstract

In the field of digital VLSI design, multi-mode circuits are the designs where the modes can be switched according to different application scenarios, and are commonly used in communication systems. In a multi-mode circuit, different modes are usually implemented by different circuits, which can lead to large circuit area consumption. For different modes, sharing their isomorphic circuit regions in the standard cell level can save the area. This goal is similar to that in the subgraph isomorphism problem, which is to check if a given graph is a subgraph of another one. However, subgraph isomorphism needs unacceptable runtime to solve as it is NP-complete. Even worse, finding the largest isomorphic regions of different circuits is a problem harder than subgraph isomorphism. In this paper, we propose a novel algorithm for efficiently finding enough isomorphic circuit regions of different digital circuits in polynomial time, and give the theoretical proof of the correctness. The experiments show that the proposed approach can save 20%-25% area on average by sharing the standard cells between 2-4 circuits, while keeping the functional correctness. The proposed algorithm also has reasonable runtime and mostly incurs negligible timing overhead.