Abstract
Due to the impressive use of analog multiplier in analog signal processing, several studies have been introduced and developed to achieve high performance multipliers. This paper presents a four-quadrant analog multiplier in current mode. It is based on the square-law characteristics of the MOS transistor in saturation region. The characteristics of proposed multiplier circuit are evaluated using ELDO simulator in 0.181μm CMOS parameters under a supply voltage of ±0.75V. The simulation results of analog multiplier show a −3db bandwidth of 460MHz, a 0.8mW of maximum power consumption and a THD of 1.2% in 1MHz.
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