0.18 [micro sign]m CMOS integrated circuit design for impedance-based structural health monitoring

Abstract

Piezoelectric materials constitute a class of intelligent materials that are helpful for monitoring the structural integrity. The principle of the piezoelectric impedance-based structural health monitoring technique is to measure the electrical impedance of a piezoelectric patch attached to a structure in a certain frequency range. Electrical impedance variations indicate physical changes in the structure due to the coupling between the electrical impedance and the mechanical impedance. Traditional methods use an impedance analyser that increases the inspection cost. The objective of this work is to introduce an electronic circuit for the piezoelectric impedance-based structural health monitoring. The circuit can monitor the electrical impedance variations of a piezoelectric patch attached to a structure. The frequency range is from 7.47 to 277.29 kHz. This frequency range covers the sensitive range of the piezoelectric structural integrity. The power consumption of the circuit is 18.15 mW. The chip area is 1.03 mm x 2.30 mm. The cost of the final design will be much lower than that of an impedance analyser. Using a wireless communication circuit, a sensor network might be established in the future.