Abstract
As CMOS scaling is approaching 0.1 mu m channel length, the authors examine a number of key device and technology issues which will ultimately determine the limit of room temperature scaling. High speed and high transconductance (750 mS/mm for n, 400 mS/mm for p) sub-0.1 mu m nMOSFET and pMOSFET devices have recently been demonstrated. P/sup +/ polysilicon gate was used on 35 AA gate oxide without boron penetration. Very low series resistances (R/sub sd/=250 Omega - mu m for nMOSFET and 500 Omega - mu m for pMOSFET) are achieved with 500-700 AA-deep n/sup +/ and p/sup +/ source-drain extensions. These results indicate that it is possible to scale CMOS devices to 0.1 mu m channel length. Beyond 0.1 mu m, however, conventional CMOS performance at room temperature levels off subject to off-current and threshold voltage requirements. A number of possibilities for further performance enhancement, such as SOI, SiGe channel, double-gate device, and low temperature CMOS are discussed. >
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