0.1-μm p/sup +/-GaAs gate HJFET's fabricated using two-step dry-etching and selective MOMBE growth techniques

Abstract

This paper reports the first successful fabrication of high-performance, 0.1-/spl mu/m p/sup +/-gate pseudomorphic heterojunction-FET's (HJFET's). By introducing the two-step dry-etching technique which compensates for the poor dry-etching resistance of PMMA, 0.1-/spl mu/m or less gate-openings with a high aspect-ratio of 3.5 in SiO/sub 2/ film are achieved. In addition, by using the gate electrode filling technique with selective MOMBE p/sup +/-GaAs growth, 0.1-/spl mu/m voidless p/sup +/-GaAs gate electrodes with a high aspect-ratio are achieved for the first time. The fabrication technology leads to a reduction of external gate fringing capacitance (Ce/sup ext//sub f/) in a T-shaped gate-structure and an improvement in gate turn-on voltage. The fabricated 0.1-/spl mu/m, T-shaped, p/sup +/-gate n-Al/sub 0.2/Ga/sub 0.8/As/In/sub 0.25/Ga/sub 0.75/As HJFET exhibits a high gate turn-on voltage (V/sub f/) of about 0.9 V, and a good gm/sub max/ of 435 mS/mm. Also, an excellent microwave performance of f/sub T/=121 GHz and f/sub max/=144 GHz is achieved due to the C/sup ext//sub f/ reduction. The technology and device show great promise for future high-speed applications, such as in power devices, MMIC's, and digital IC's.