Abstract
This study entailed the development of a K-Band power amplifier (PA). The proposed PA was implemented and verified using a 65-nm bulk CMOS process. The PA was designed with two stages to obtain sufficient gain in the K band. The PA had a chip area of 0.93×0.47 mm2 including RF and DC pads. The manufactured power amplifier design had a maximum saturation power of 22.4∼22.7 dBm in the 19–21 GHz frequency band, and a power added efficiency (PAE) of 39 %∼40 %. In the two-tone simulation results, the linear power and efficiency levels satisfying third-order inter-modulation distortion (IMD3) below −30 dBc were confirmed to be 16∼17 dBm and 24%∼26 % in the 19∼21 GHz frequency band, respectively.
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