シリコン/ガラス構造におけるDeep-RIEプロセスの開発

Abstract

For devices with bonded silicon and glass structures fabricated by deep-RIE, it is important to avoid damage at the silicon backside and sidewall during through-wafer etching in order to ensure reliability of devices. The silicon backside damage is caused by charge accumulation at the glass surface. This paper reports the novel method to avoid the processing damage occurred in silicon structures of accelerometers by means of an electrically conducting layer patterned onto the glass and connected with the silicon. The positions of silicon damage in the structural layout were identified without destruction of samples by using transparent indium tin oxide (ITO) films as the electrically conducting layer. From the experiments, it was found that there exists silicon damage caused by charge accumulation at the silicon islands isolated by deep-RIE and we present important rules for mask layout when utilizing this method. Finally, the improved results of shock tests are briefly shown.