Abstract
This paper explains how the temperature of Si wafers during polishing affects their flatness after polishing. During the polishing operation, the temperature distribution of the wafer was measured using thermistor sensors (0.1 K accuracy) attached to the wafer opposite the surface being polished. It is made clear that this distribution is affected by the pouring method and temperature of the polishing reagent. The temperature near the center of the Si wafer during polishing is about 1.0 K higher than that of the surrounding area. As a result, chemical action is activated, increasing the stock removal rate at the center, and the polishing wafer is out of flat by 0.6-1.2μm in a concave direction.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: Journal of the Japan Society for Precision Engineering
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
