Abstract
The effects of dead-time and offset error, which cause output current distortion in single-phase grid-connected inverters are investigated this paper. Offset error is typically generated by measuring phase current, including the voltage unbalance of analog devices and non-ideal characteristics in current measurement paths. Dead-time inevitably occurs during generation of the gate signal for controlling power semiconductor switches. Hence, the performance of the grid-connected inverter is significantly degraded because of the current ripples. The current and voltage, including ripple components on the synchronous reference frame and stationary reference frame, are analyzed in detail. An algorithm, which has the proportional resonant controller, is also proposed to reduce current ripple components in the synchronous PI current regulator. As a result, computational complexity of the proposed algorithm is greatly simplified, and the magnitude of the current ripples is significantly decreased. The simulation and experimental results are presented to verify the usefulness of the proposed current ripple reduction algorithm.
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