Разработка микроконтроллерного FMU ядра на базе ПЛИС для научной космической аппаратуры

Abstract

A FMU (Flexible Microcontroller Unit) model of the core of a domestic FPGA is proposed with the purpose of obtaining characteristics superior in speed and type of data processing over modern domestic and foreign microcontrollers. The FMU core and its corresponding peripherals are designed on FPGA, which makes the architecture of the entire microcontroller flexible and allows its characteristics to be varied without the need to acquire other chips. The entire architecture is a single configuration file, written in the Verilog HDL and combining the core and peripheral blocks. At the request of the user, the number of peripheral modules сan be either increased or reduced. Parallel (multicore) data processing is also available, which function is absent in modern microcontrollers. The program for the configured microcontroller is written in a C-style language, which is converted into a binary package of a program loaded separately into the program memory of the microcontroller in question. To convert the source code into such a package, a corresponding C++ compiler was developed. The paper provides a block diagram of the kernel architecture, time diagrams of various packages and instructions, as well as a list of kernel commands. The test results presented in the paper demonstrate small time expenditures on executing some instructions for working with internal and external RAM. Conclusions are formulated and brief characteristics of the core are given.