Маршрут проектирования и тестирование аналоговых блоков RTL модели программно-аналитического комплекса САПР

Abstract

The article discusses the stages of development of domestic CAD designed for the design of various digital devices of microelectronics. The presented works were carried out by VGLTU together with ROSELECTRONICS Holding. An important process in the development of CAD is the design of analog RTL (Register Transfer Level) blocks that determine the logic of the device functioning at a low level. This development needs to build a design route and test RTL blocks, for the practical implementation of which the programming languages of the Verilog and SystemVerilog microcontrollers were used. At the beginning, the CAD testing route is described in detail with a detailed description of its stages. Then the cells of functional SF blocks were generated, and the algorithm of its generation was given. The distinctive features of the conducted analysis is the ability to conduct testing for analog blocks. At the end, various testing methods were used, including functional testing, performance testing at various loads and verification of compliance with specifications. Also, the simulation of the operation of the units at different operating frequencies and with changing parameters was carried out. In conclusion, we described the process of installing CAD on the developer's workstation, which is necessary for the correct use of the PCB in the Cadence environment.