Особливості блока керування для кореляційного оброблення зображень

Abstract

The widespread introduction of mobile robots in various areas of human activity requires their further improvement and modernization of basic systems in their composition. The most involved in this case are the means of technical vision in the onboard systems of mobile robots, as well as the associated control blocks. When the mobile robot functions in automatic mode, it is necessary to take into account several features and limitations that are due to the nature of the practical tasks. For the control block, first of all, it is to ensure the speed of operation and compactness of implementation with a focus on FPGA technology. In this paper, these aspects of the construction of the control block are considered in terms of the implementation of correlation processing of static digital (binary) images. As a specific example, an optoelectronic system with a correlation binary matrix and a matrix of LEDs to visualize the generated optical correlation relief was chosen. Such systems are most often part of onboard control systems for mobile robots and are designed to detect and identify objects. The structure of the control block is proposed, taking into account the peculiarities of correlation processing in the optoelectronic system. The control block contains three counters: a clock counter, an address counter for reading from the reference memory, an address counter for an offset in the correlation matrix, and a control device. The control device as a part of the control block as the microprogram automaton (MPA) with the use of features of synthesis of the R- automaton is constructed. A feature of the R-machine is the implementation of its storage part on the shift register (R) in contrast to the parallel registers (T) and counters (ST). Such an approach simplifies the combinational part of the MPA with the possibility of increasing its regular memory based on the shift register. This allows you to effectively implement such structures in a single chip with FPGA architecture.