Abstract
The paper presents an overview of approaches used in verifying correctness of multicore microprocessors caches. Common properties of memory subsystem devices and those specific to caches are described. We describe the method to support memory consistency in a system using cache coherence protocol. The approaches for designing a test system, generating valid stimuli and checking the correctness of the device under verification (DUV) are introduced. Adjustments to the approach for supporting generation of out-of-order test stimuli are provided. Methods of the test system development on different abstraction levels are presented. We provide basic approach to device behavior checking - implementing a functional reference model, reactions of this model could be compared to device reactions, miscompare denotes an error. Methods for verification of functionally nondeterministic devices are described: the «gray box» method based on elimination of nondeterministic behavior using internal interfaces of the implementation and the novel approach based on the dynamic refinement of the behavioral model using device reactions. We also provide a way to augment a stimulus generator with assertions to further increase error detection capabilities of the test system. Additionally, we describe how the test systems for devices, that support out of order execution, could be designed. We present the approach to simplify checking of nondeterministic devices with out-of-order execution of requests using a reference order of instructions. In conclusion, we provide the case study of using these approaches to verify caches of microprocessors with “Elbrus” architecture and “SPARC-V9” architecture.
Highlights
The key feature of modern microprocessor architecture is multicoreness — combining several computational cores on a single system on a chip (SOC)
This paper addresses the problem of stand-alone verification of microprocessor caches of different levels
The approaches described above were used for stand-alone verification of L2cache[3] and the L3-cache[6] of the microprocessor with “Elbrus” architecture and L1Data-cache (L1dc) of the microprocessor with “SPARC-V9” architecture
Summary
The key feature of modern microprocessor architecture is multicoreness — combining several computational cores on a single system on a chip (SOC). To optimize the design and the implementation of coherency protocol, caches can include a local directory — the device which keeps information on states of data in different components of the memory subsystem. Two main approaches to functional verification of microprocessors are formal verification and simulation-based methods [2]. One of the approaches to microprocessor verification is execution of test programs on the microprocessor model and on the reference implementation of its instruction set, and comparison between them. This paper addresses the problem of stand-alone verification of microprocessor caches of different levels.
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