Численное моделирование низковольтных логических вентилей на базе полевых нанотранзисторов с переменным диаметром рабочей области

Abstract

The issues of TCAD simulation of low-voltage logic gates made on SOI CMOS nanotransistors with cylindrical geometry with a fully enclosing gate with a variable diameter of the working area are discussed. Changing the geometry of the working area compared to the usual cylindrical shape improves the electrophysical characteristics and allows you to compensate for the limitations that arise as a result of scaling. Numerical studies of conical prototypes were carried out using mathematical simulation performed using the TCAD instrument technological simulation program based on the n- and p-type nanotransistor models developed by TCAD. The simulation results demonstrate improved electrostatic characteristics. The conical structure in the control voltage range from 0 to 0.6 V is characterized by a higher transistor current, a maximum Ion/Ioff current ratio, a low leakage current and a slope of the subthreshold characteristic close to the theoretical chapel. The dynamic characteristics of the developed physical models of the inverter and the chain of 11 inverters are numerically investigated for the optimized ratio of the diameters of the working area of 8.1/10 nm and the gate length of 25 nm. At control voltages of 0.6 V and a frequency of 25 GHz, the inverter model predicts a maximum switching delay of 1.5 ps, the limit level of active power of 0.21 μW, static 4.4 pW. The active power consumed by the circuit consisting of 11 inverters is 2.34 μW at control voltages of 0.6 V.