Computer Architecture Research Articles

Development and Implementation of Visualization of CPU Components using AR

Augmented Reality (AR) technology presents innovative solutions for visualizing complex concepts and systems. This paper investigates the utilization of AR in the visualization of CPU (Central Processing Unit) components, with the objective of augmenting comprehension and learning within computer architecture. By developing an AR application, CPU components are depicted in three dimensions, enabling users to interactively explore and comprehend their functionalities and interconnections. The paper delineates the design and execution of the AR system and discusses its potential advantages for education, training, and technical problem-solving in computer science and engineering. Keywords: Augmented Reality, CPU Components, Visualization, Computer Architecture.

Survey on Redundancy Based-Fault tolerance methods for Processors and Hardware accelerators - Trends in Quantum Computing, Heterogeneous Systems and Reliability

Rapid progress in the CMOS technology for the past 25 years has increased the vulnerability of processors towards faults. Subsequently, focus of computer architects shifted towards designing fault-tolerance methods for processor architectures. Concurrently, chip designers encountered high order challenges for designing fault tolerant processor architectures. For processor cores, redundancy-based fault tolerance methods for fault detection at core level, micro-architectural level ,thread level , and software level are discussed. Similar applicable redundancy-based fault tolerance methods for cache memory, and hardware accelerators are presented in the article. Recent trends in fault tolerant quantum computing and quantum error correction are also discussed. The classification of state-of-the-art techniques is presented in the survey would help the researchers to organize their work on established lines.

Edge HPC Architectures for AI-Based Video Surveillance Applications

The introduction of artificial intelligence (AI) in video surveillance systems has significantly transformed security practices, allowing for autonomous monitoring and real-time detection of threats. However, the effectiveness and efficiency of AI-powered surveillance rely heavily on the hardware infrastructure, specifically high-performance computing (HPC) architectures. This article examines the impact of different platforms for HPC edge servers, including x86 and ARM CPU-based systems and Graphics Processing Units (GPUs), on the speed and accuracy of video processing tasks. By using advanced deep learning frameworks, a video surveillance system based on YOLO object detection and DeepSort tracking algorithms is developed and evaluated. This study thoroughly assesses the strengths, limitations, and suitability of different hardware architectures for various AI-based surveillance scenarios.

Negative Differential Resistance in Conical Nanopore Iontronic Memristors.

Emerging ion transport dynamics with memory effects at nanoscale solution-substrate interfaces offers a unique opportunity to overcome the bottlenecks in traditional computational architectures, trade-offs in selectivity and throughput in separation, and electrochemical energy conversions. Negative differential resistance (NDR), a decrease in conductance with increasing potential, constitutes a new function from the perspective of time-dependent instead of steady-state nanoscale electrokinetic ion transport but remains unexplored in ionotronics to develop higher-order complexity and advanced capabilities. Herein, NDR is introduced in hysteretic and rectified ion transport through single conical nanopipettes (NPs) as ionic memristors. Deterministic and chaotic behaviors are controlled via an electric field as the sole stimulus. The NDR arises fundamentally from the availability and redistribution of the ionic charges during the hysteretic and rectified transport at asymmetric nanointerfaces. The elucidated mechanism is generalizable, and the drastically simplified operations enable tunable state-switching dynamics with higher-order complexity besides the first-order synaptic functions in multiple excitatory and inhibitory states.

From cloud and fog computing to federated-fog computing: A comparative analysis of computational resources in real-time IoT applications based on semantic interoperability

In contemporary computing paradigms, the evolution from cloud computing to fog computing and the recent emergence of federated-fog computing have introduced new challenges pertaining to semantic interoperability, particularly in the context of real-time applications. Fog computing, by shifting computational processes closer to the network edge at the local area network level, aims to mitigate latency and enhance efficiency by minimising data transfers to the cloud. Building upon this, federated-fog computing extends the paradigm by distributing computing resources across diverse organisations and locations, while maintaining centralised management and control. This research article addresses the inherent problematics in achieving semantic interoperability within the evolving architectures of cloud computing, fog computing, and federated-fog computing. Experimental investigations are conducted on a diverse node-based testbed, simulating various end-user devices, to emphasise the critical role of semantic interoperability in facilitating seamless data exchange and integration. Furthermore, the efficacy of federated-fog computing is rigorously evaluated in comparison to traditional fog and cloud computing frameworks. Specifically, the assessment focuses on critical factors such as latency time and computational resource utilisation while processing real-time data streams generated by Internet of Things (IoT) devices. The findings of this study underscore the advantages of federated-fog computing over conventional cloud and fog computing paradigms, particularly in the realm of real-time IoT applications demanding high performance (lowering CPU usage to 20%) and low latency (with picks up to 300ms). The research contributes valuable insights into the optimisation of processing architectures for contemporary computing paradigms, offering implications for the advancement of semantic interoperability in the context of emerging federated-fog computing for IoT applications.

An Efficient FHE-Enabled Secure Cloud–Edge Computing Architecture for IoMT Data Protection With its Application to Pandemic Modeling

An Efficient FHE-Enabled Secure Cloud–Edge Computing Architecture for IoMT Data Protection With its Application to Pandemic Modeling

Quantum Control Machine: The Limits of Control Flow in Quantum Programming

Quantum algorithms for tasks such as factorization, search, and simulation rely on control flow such as branching and iteration that depends on the value of data in superposition. High-level programming abstractions for control flow, such as switches, loops, higher-order functions, and continuations, are ubiquitous in classical languages. By contrast, many quantum languages do not provide high-level abstractions for control flow in superposition, and instead require the use of hardware-level logic gates to implement such control flow. The reason for this gap is that whereas a classical computer supports control flow abstractions using a program counter that can depend on data, the typical architecture of a quantum computer does not analogously provide a program counter that can depend on data in superposition. As a result, the complete set of control flow abstractions that can be correctly realized on a quantum computer has not yet been established. In this work, we provide a complete characterization of the properties of control flow abstractions that are correctly realizable on a quantum computer. First, we prove that even on a quantum computer whose program counter exists in superposition, one cannot correctly realize control flow in quantum algorithms by lifting the classical conditional jump instruction to work in superposition. This theorem denies the ability to directly lift general abstractions for control flow such as the λ-calculus from classical to quantum programming. In response, we present the necessary and sufficient conditions for control flow to be correctly realizable on a quantum computer. We introduce the quantum control machine, an instruction set architecture featuring a conditional jump that is restricted to satisfy these conditions. We show how this design enables a developer to correctly express control flow in quantum algorithms using a program counter in place of logic gates.

A variational reformulation of molecular properties in electronic-structure theory.

Conventional quantum-mechanical calculations of molecular properties, such as dipole moments and electronic excitation energies, give errors that depend linearly on the error in the wave function. An exception is the electronic energy, whose error depends quadratically on the error in wave function. We here describe how all properties may be calculated with a quadratic error, by setting up a variational Lagrangian for the property of interest. Because the construction of the Lagrangian is less expensive than the calculation of the wave function, this approach substantially improves the accuracy of quantum-chemical calculations without increasing cost. As illustrated for excitation energies, this approach enables the accurate calculation of molecular properties for larger systems, with a short time-to-solution and in a manner well suited for modern computer architectures.

Comparing cognition across major transitions using the hierarchy of formal automata.

The evolution of cognition can be understood in terms of a few major transitions-changes in the computational architecture of nervous systems that changed what cognitive capacities could be evolved by downstream lineages. We demonstrate how the idea of a major cognitive transition can be modeled in terms of where a system's effective computational architecture falls on the well-studied hierarchy of formal automata (HFA). We then use recent work connecting artificial neural networks to the HFA, which provides a way to make the structure-architecture link in natural systems. We conclude with reflections on the power and the challenges of traditional thinking when applied to neural architectures. This article is categorized under: Cognitive Biology > Evolutionary Roots of Cognition Psychology > Comparative Philosophy > Foundations of Cognitive Science.

Room Temperature Quantum Control of N‐Donor Electrons at Si/SiO2 Interface

AbstractThe manuscript theoretically discusses various important aspects for donor atom based single qubit operations in silicon (Si) quantum computer architecture at room temperature using a single nitrogen (N) deep‐donor close to the Si/SiO2 interface. Quantitative investigation of room temperature single electron shuttling between a single N‐donor atom and the interface is the focus of attention under the influence of externally applied electric and magnetic field. To apprehend the realistic experimental configurations, central cell correction along with effective mass approach is adopted throughout the study. Furthermore, a detailed discussion currently explores the significant time scales implicated in the process and their suitability for experimental purposes. Theoretical estimates are also provided for all the external fields required to successfully achieve coherent single electron shuttling and their stable maintenance at the interface as required. The results presented in this work offer practical guidance for quantum electron control using N‐donor atoms in Si at room temperature.

Design and analysis of an adaptive radiation resilient RRAM subsystem for processing systems in satellites

AbstractAmong the numerous benefits that novel RRAM devices offer over conventional memory technologies is an inherent resilience to the effects of radiation. Hence, they appear suitable for use as a memory subsystem in a computer architecture for satellites. In addition to memory devices resistant to radiation, the concept of applying protective measures dynamically promises a system with low susceptibility to errors during radiation events, while also ensuring efficient performance in the absence of radiation events. This paper presents the first RRAM-based memory subsystem for satellites with a dynamic response to radiation events. We integrate this subsystem into a computing platform that employs the same dynamic principles for its processing system and implements modules for timely detection and even prediction of radiation events. To determine which protection mechanism is optimal, we examine various approaches and simulate the probability of errors in memory. Additionally, we are studying the impact on the overall system by investigating different software algorithms and their radiation robustness requirements using a fault injection simulation. Finally, we propose a potential implementation of the dynamic RRAM-based memory subsystem that includes different levels of protection and can be used for real applications in satellites.

Fast polynomial multiplication using matrix multiplication accelerators with applications to NTRU on Apple M1/M3 SoCs

Efficient polynomial multiplication routines are critical to the performance of lattice-based post-quantum cryptography (PQC). As PQC standards only recently started to emerge, CPUs still lack specialized instructions to accelerate such routines. Meanwhile, deep learning has grown immeasurably in importance. Its workloads call for teraflops-level of processing power for linear algebra operations, mainly matrix multiplication. Computer architects have responded by introducing ISA extensions, coprocessors and special-purpose cores to accelerate such operations. In particular, Apple ships an undocumented matrix-multiplication coprocessor, AMX, in hundreds of millions of mobile phones, tablets and personal computers. Our work repurposes AMX to implement polynomial multiplication and applies it to the NTRU cryptosystem, setting new speed records on the Apple M1 and M3 systems-on-chip (SoCs): polynomial multiplication, key generation, encapsulation and decapsulation are sped up by 1.54 – 3.07 × , 1.08 – 1.33 × , 1.11 – 1.50 × and 1.20 – 1.98 × , respectively, over the previous state-of-the-art.

Visual Exploratory Analysis for Designing Large-Scale Network-on-Chip Architectures: A Domain Expert-Led Design Study.

Visualization design studies bring together visualization researchers and domain experts to address yet unsolved data analysis challenges stemming from the needs of the domain experts. Typically, the visualization researchers lead the design study process and implementation of any visualization solutions. This setup leverages the visualization researchers' knowledge of methodology, design, and programming, but the availability to synchronize with the domain experts can hamper the design process. We consider an alternative setup where the domain experts take the lead in the design study, supported by the visualization experts. In this study, the domain experts are computer architecture experts who simulate and analyze novel computer chip designs. These chips rely on a Network-on-Chip (NOC) to connect components. The experts want to understand how the chip designs perform and what in the design led to their performance. To aid this analysis, we develop Vis4Mesh, a visualization system that provides spatial, temporal, and architectural context to simulated NOC behavior. Integration with an existing computer architecture visualization tool enables architects to perform deep-dives into specific architecture component behavior. We validate Vis4Mesh through a case study and a user study with computer architecture researchers. We reflect on our design and process, discussing advantages, disadvantages, and guidance for engaging in a domain expert-led design studies.

A parallel and performance portable implementation of a full-field crystal plasticity model

We have developed a parallel implementation of an Elasto-Viscoplastic Fast Fourier Transform-based (EVPFFT) micromechanical solver to enable computationally efficient crystal plasticity modeling for polycrystalline materials. Our primary focus lies in achieving performance portability, allowing a single EVPFFT implementation to run optimally on various homogeneous architectures, including multi-core Central Processing Units (CPUs), as well as on heterogeneous computer architectures comprising multi-core CPUs and Graphics Processing Units (GPUs) from different vendors. To accomplish this goal, we have leveraged MATAR, a C++ software library that simplifies the creation and utilization of multidimensional dense or sparse matrix and array data structures. These data structures are designed to be portable across diverse architectures through the use of Kokkos, a performance-portable library. Additionally, we have employed the Message Passing Interface (MPI) to efficiently distribute the computational workload among processors. The heFFTe (Highly Efficient FFT for Exascale) library is used to facilitate the performance portability of the fast Fourier transforms (FFTs) computation. The computational performance of EVPFFT is evaluated and presented in terms of parallel scalability and simulation runtime on different high-performance computing (HPC) architectures. The utility of the developed framework to efficiently simulate the micro-mechanical fields in polycrystalline microstructures in engineering applications is discussed. Program summaryProgram Title: EVPFFTCPC Library link to program files:https://doi.org/10.17632/2k8579fyyv.1Developer's repository link:https://github.com/lanl/FierroLicensing provisions: BSD 3-Clause LicenseProgramming language: C++External routines/libraries: MPI, Kokkos, MATAR, HeFFTe, HDF5Nature of problem: EVPFFT is a crystal plasticity code designed to compute micro-mechanical fields within a polycrystalline representative volume element (RVE) and predict the macroscale response of the RVE.Solution method: EVPFFT uses the periodic Green's function method in Fourier space to solve the field equations of static stress equilibrium in a periodic spatial domain.

Cloud-based urgent computing for forest fire spread prediction

Forest fires cause every year damages to biodiversity, atmosphere, and economy activities. Forest fire simulation have improved significantly, but input data describing fire scenarios are subject to high levels of uncertainty. In this work the two-stage prediction scheme is used to adjust unknown parameters. This scheme relies on an input data calibration phase, which is carried over following a genetic algorithm strategy. The calibrated inputs are then pipelined into the actual prediction phase. This two-stage prediction scheme is leveraged by the cloud computing paradigm, which enables high level of parallelism on demand, elasticity, scalability and low-cost. In this paper, all the models designed to properly allocate cloud resources to the two-stage scheme in a performance-efficient and cost-effective way are described. This Cloud-based Urgent Computing (CuCo) architecture has been tested using, as study case, an extreme wildland fire that took place in California in 2018 (Camp Fire).

Test Environment for Verifying Quantum Algorithms and Controlling SINARA Real-time Modules

This paper describes the process of creating and using a quantum computing environment. It also discusses the manner in which first quantum experiments using mathematical models, simulators or commercially available quantum computers may be conducted. In addition, it explains how the available quantum algorithms may be understood and applied. Finally, the role of real-time systems and their control in the architecture of a quantum computer is described.

The Role of the Supercomputer in the Modern World of Innovative Technologies

What is a supercomputer and why is it needed? What place does it occupy among computing equipment? Thanks to this article, we will determine the evolution and role of the supercomputer in the modern world and in the life of an average citizen. A supercomputer is a class of the most powerful computer systems available, which are evaluated in comparison with currently existing general purpose computer systems and the level of technology development. In general, the term "supercomputer" refers to a complex of server computers. All of them are connected to each other and work in parallel through a high-speed network. The similarity of a home computer and a supercomputer lies in their functions – data storage and processing, belonging to the same von Neumann architecture (the architecture of computing machines, the feature of which is the joint storage of data and machine commands in cells of the same memory). But the difference is huge in quantitative characteristics: these are the arrays of data that can be processed on these devices and the speed of performing the assigned tasks. By the way, a new unit of measurement – FLOPS – was proposed for measuring the speed of supercomputers. It is thanks to this value that performance is measured - the higher the number, the more powerful the computer is and which serves as the basis for ranking supercomputers. Today, supercomputers help solve a number of tasks in various fields – medicine, physics, mathematics, energy, etc. and are considered advanced computing technology. Traditionally, supercomputers are not considered rare: their development is ongoing and they bring a lot of benefits in many areas. In the future, powerful computing machines can become the main assistants in fields closely related to machine learning and artificial intelligence. Keywords: supercomputer, development evolution, computer architecture, FLOPS.

IMPROVED RENDERING METHOD OF SKELETAL ANIMATION ON CONTROL POINTS BASE

Current research builds on an investigation of skeletal animation methods, focusing on the use of control points for managing limb movements. It thoroughly considers the relevance and significance of the chosen topic and its impact on creating realistic and effective visual projects in the modern world of digital graphics and reproduction. The research includes an analysis of the impact of sample quantity on the frame transitions smoothness and the rendering time to achieve a balance between quality and efficiency. It also involves refining the method through adaptation for execution on a GPU graphic processor. Studied Blender 3D engines (EEEVE and Cycles) allowed to analyze rendering performance on different computational architectures – CPU and GPU depending on sample values (60 and 128), frame number (250, 500, and 1000), and also the frame frequency at a rate of 30 frames per second. The goal of the research was an achievement of optimal balance between performance and realism in animation details reproduction. Three experiments were done to reach this goal and make the following conclusion: graphical processor utilization through the Cycles engine demonstrated a rendering acceleration of 43%, ranging from minimal to maximum settings. In the same time, the acceleration of the hybrid system via the EEVEE engine showed an acceleration of 15.2% only.

Hybrid programming-model strategies for GPU offloading of electronic structure calculation kernels.

To address the challenge of performance portability and facilitate the implementation of electronic structure solvers, we developed the basic matrix library (BML) and Parallel, Rapid O(N), and Graph-based Recursive Electronic Structure Solver (PROGRESS) library. The BML implements linear algebra operations necessary for electronic structure kernels using a unified user interface for various matrix formats (dense and sparse) and architectures (CPUs and GPUs). Focusing on density functional theory and tight-binding models, PROGRESS implements several solvers for computing the single-particle density matrix and relies on BML. In this paper, we describe the general strategies used for these implementations on various computer architectures, using OpenMP target functionalities on GPUs, in conjunction with third-party libraries to handle performance critical numerical kernels. We demonstrate the portability of this approach and its performance in benchmark problems.

Advanced Framework for Multi-Modal Healthcare Data Integration: Leveraging HPC with GPU Computing and CNN Architecture in CDSS

In this study, we shall be looking at the challenges involved in integrating multi-modal healthcare data in the clinical decision support systems (CDSS). We propose the Automated Multi-Modal Data Integration (AMMI-CDSS) algorithm, which will utilize the latest high-performance computing (HPC) techniques such as the Convolutional Neural Network (CNN) architecture and the Graphics Processing Unit (GPU) computing to provide precise and rapid analysis. Which features will be extracted, multi-modal data will be merged, data will be prepared and algorithms developed in a distributed computing environment. We illustrate how AMMI-CDSS through the use of real world datasets such as wearable sensors data, medical imaging, genetic data, and electronic health records (EHRs), can improve the clinical decision support. By performing harmonization of the diverse data sources into a unique dataset after thorough data preprocessing and complex calculations, AMMI-CDSS provides the analysis with better quality and coherence.
 Our study allow us to make conclusion about how HPC-based CDSS models can be compared to conventional machine learning ones using their scalability and performance as key metrics. We enrich CDSS with the methodical framework for one-by-one testing and evaluation of proposed models and multi-modal healthcare data analysis. Future research might explore novel methods for integrating diverse types of healthcare data, as well as enhancing the HPC-based CDSS models by keeping them up-to-date.