The increasing integration of renewable energy systems (RESs) such as solar and wind into modern power grids using converter‐based, inertia‐less interfaces poses serious frequency stability challenges. This is due to reduced system inertia conventionally provided by synchronous generators. This paper proposes an innovative solution using an adaptive grid‐forming controller (AGFC), designed to emulate and adapt virtual inertia and damping in real time. The AGFC uniquely combines grid‐forming virtual inertia damping control with an adaptive DC link voltage regulation loop, coordinated by a genetic algorithm–optimized proportional integral (GA‐PI) controller. Key innovation lies in employing the GA‐PI control to dynamically manage DC link energy exchange during grid disturbances. Through optimized GA‐PI tuning, rapid adjustment of control parameters is achieved to maintain system stability during sudden load changes. MATLAB/Simulink simulations demonstrate that the proposed AGFC substantially mitigates frequency deviation, rate of change of frequency, and frequency settling time under transient conditions. Compared with conventional grid‐forming control without adaptive DC link management, the designed AGFC depicts superior resilience and adaptability to load disturbances. It enables inverters to autonomously establish voltage and frequency references while providing synchronous generator‐like stabilization. The results demonstrate that the proposed framework enhances the grid’s inertial response and dynamic stability for converter‐interfaced RES. Future research will explore scaling the AGFC for multiarea grids and applying advanced parameter optimization to larger systems. This is expected to further improve system‐wide frequency regulation and stability.

A compact single asymmetric coplanar waveguide feed (ACPW‐fed) dual circularly polarized microstrip antenna that operates at 1.8, 3.9, and 5.2 GHz in the entire operating frequency band 600 MHz–6 GHz for the radar detection of the improvised explosive devices (IEDs) carried by a person is introduced. The proposed novel quasi‐omnidirectional antenna consists of single sided rectangular ring microstrip patch antenna. L‐shaped slots are etched at the two opposite corners of the rectangular ring, introducing new resonance and circular polarization waves at the mid and upper bands, respectively. The achieved dual half‐rectangular ring patch antenna (DHRR‐patch) is loaded with strips of various shapes delicately placed at the center of the radiator, providing new resonance at the upper band and the improvement of the CP features. The matching technique designed based on CPW 50 Ω microstrip transmission line combined with the dual broad band matching techniques through quarter‐wave transformer in conjunction with open stubs and distributed lumped element method constitutes the novelty of the study. Based on quasi‐TEM mn (q‐TEM mn ) mode, ACPW‐fed and CP‐slots are employed to generate CP radiations at the q‐TEM 11 and q‐TEM 21 modes, respectively, while the ground plane width is optimized to enhance axial ratio bandwidth (AR‐BW). Input impedance and radiation pattern calculations of the conventional structure using transmission line and cavity model‐based q‐TEM 01 mode are conducted, respectively. Numerical experiments of the studied monolayer antenna are carried out using Advanced Design System (ADS) Version 2009 environment software employing internal one‐port option to excite the antenna. The prototype of the proposed antenna with a compact dimension (0.27 λ g × 0.38 λ g × 0.02 λ g at 1.8 GHz where λ g is the guided wavelength of the q‐TEM 01 mode) is fabricated on high loss laminate FR4 substrate of volume 43 × 38 × 1.6 (mm 3 ) and relative dielectric constant of 4.4 with simple laboratory‐based traditional printed circuit board (PCB) etching process. Measurement results show a fractional impedance bandwidth (FIBW) of 11.1%, 5.9%, and 7.1%, axial ratio (AR) of 4.6, 2.2, and 0.5 dB, and peak gain of 3.7, 4.7, and 6.1 dBic at 1.8, 4.0, and 5.2 GHz, respectively, demonstrating its suitability for IED detection applications. To verify the efficiency of the proposed model, measured results are compared with the simulated results and good agreement has been established.

Brushless DC (BLDC) motor drives are extensively preferred in the automotive industry for their high torque‐to‐weight ratio. In conventional BLDC drives, the torque ripples are high due to 120° conduction mode operation and nonideal back EMF. To minimize the torque ripple in BLDC drives, a flux trajectory is employed based on the extension Park transformation d‐q axis frame. This article introduces a control scheme for BLDC drives that integrate maximum torque per ampere (MTPA) with pseudo–field‐oriented control (FOC). This approach gets an optimal reference d‐axis current () that optimize the current magnitude ) and minimize copper loss. Furthermore, the 180o conduction mode is used to minimize the torque ripple and provide high dynamic performance of drives. The efficacy of the proposed MTPA‐based pseudo‐FOC strategy is experimentally validated by employing a 0.75‐kW BLDC motor drive using real‐time interface controller dSPACE 1202 and Danfoss VLT 302 converter.

Nanosatellites have opened up significant opportunities for small and medium enterprises and academic institutions in space technology, driving demand for compact, high‐performance antennas. This study presents a miniaturized, right‐handed circularly polarized (RHCP) V‐shaped patch array antenna, integrated with a matched feeding network, tailored for nanosatellite applications. The innovative design achieves a compact 13 × 13 cm2 footprint while delivering a high gain of 8.95 dBi, a wide −3 dB beamwidth of 55°, and an axial ratio (AR) of less than 5 dB over a 61° beamwidth. A −10‐dB return loss (RL) bandwidth of 80 MHz at 2.45 GHz ensures reliable performance within the S‐band. The proposed design offers significant advantages over traditional antennas, including enhanced polarization stability and efficient communication links under orientation shifts, making it ideal for telemetry, tracking, control (TT&C); Earth observation; and remote sensing missions in nanosatellites. These results highlight the antenna’s potential to advance satellite communication systems in compact and constrained environments.

Reconfigurable computing (RC) theory aims to take advantage of the flexibility of general‐purpose processors (GPPs) alongside the performance of application specific integrated circuits (ASICs). Numerous RC architectures have been proposed since the 1960s, but all are struggling to become mainstream. The main factor that prevents RC to be used in general‐purpose CPUs, GPUs, and mobile devices is that it requires extensive knowledge of digital circuit design which is lacked in most software programmers. In an RC development, a processor cooperates with a reconfigurable hardware accelerator (HA) which is usually implemented on a field‐programmable gate arrays (FPGAs) chip and can be reconfigured dynamically. It implements crucial portions of software (kernels) in hardware to increase overall performance, and its design requires substantial knowledge of digital circuit design. In this paper, a novel RC architecture is proposed that provides the exact same instruction set that a standard general‐purpose RISC microprocessor (e.g., ARM Cortex‐M0) has while automating the generation of a tightly coupled RC component to improve system performance. This approach keeps the decades‐old assemblers, compilers, debuggers and library components, and programming practices intact while utilizing the advantages of RC. The proposed architecture employs the LLVM compiler infrastructure to translate an algorithm written in a high‐level language (e.g., C/C++) to machine code. It then finds the most frequent instruction pairs and generates an equivalent RC circuit that is called miniature accelerator (MA). Execution of the instruction pairs is performed by the MA in parallel with consecutive instructions. Several kernel algorithms alongside EEMBC CoreMark are used to assess the performance of the proposed architecture. Performance improvement from 4.09% to 14.17% is recorded when HA is turned on. There is a trade‐off between core performance and combination of compilation time, die area, and program startup load time which includes the time required to partially reconfigure an FPGA chip.

On‐chip caches occupy a significant portion of modern processors, making them increasingly vulnerable to soft errors as technology scales. While data arrays often receive robust protection via error‐correcting codes (ECCs), metadata elements such as tag fields and status bits remain inadequately protected despite their critical role in ensuring memory integrity. This paper proposes two lightweight techniques to enhance cache metadata reliability: (1) a robust three‐bit encoding scheme for status bits that tolerates single‐bit flips without data corruption and (2) a selective tag replication scheme for dirty cache blocks, enabling reliable recovery from single‐bit errors in tag arrays. Simulation results on SPEC 2006 benchmarks show that our approach recovers 97.3% of injected soft errors in cache metadata, outperforming conventional SECDED protection (93.8%) with significantly lower overhead. The proposed design incurs only 0.50% area and 1.67% dynamic power overhead on a data L1 cache. Moreover, the proposed techniques can be extended to support common cache coherence protocols in multicore systems with minimal modification.

In order to realize rapid and accurate early warning of college students’ psychological crisis, an improved emotion recognition method based on the YOLOv8 model is proposed. Firstly, a depth‐separable deep convolutional module is introduced based on YOLOv8 algorithm to improve the detection effect of facial expression details. Secondly, a new detection frame regression loss is introduced to improve the accuracy of college students’ emotion recognition. Finally, the effectiveness of the proposed method is verified on a standard emotion recognition public dataset. The experimental results show that compared with several variants of YOLOv8, our model is significantly superior to other comparison methods and the overall accuracy of emotion recognition reaches 0.784. Our method has better stability and sustainability. The accurate basis can be provided to college students’ psychological early warning.

The battery power storage system plays a crucial role in converting electric energy into chemical energy and storing it for future use. It finds wide applications in electronic devices, electric vehicles, power storage stations, aerospace, and other industries. Consequently, it has become a significant research area in clean energy transformation and energy management. To achieve fast charging and discharging, improve energy utilization efficiency, and promote environmental friendliness, this paper proposes a novel battery hybrid power storage system that combines supercapacitor technology with lithium‐ion technology. The objective of this system is to address the issue of high investment costs by introducing a simplified power storage configuration that enhances grid stability. This paper considers the characteristics of batteries to develop a power storage configuration plan that is both reliable and cost‐effective. By leveraging the dynamic adjustability of lithium batteries and the high storage capacity of supercapacitors, and employing the whale optimization algorithm (WOA) and a simulated annealing strategy with adaptive weight, an integrated power storage and capacity configuration scheme is derived. The scheme is constructed based on actual demand and an objective function that minimizes the average usage cost of power storage. Furthermore, the proposed scheme is evaluated using real‐world data from a renewable energy field to assess its effectiveness in improving power storage configuration and verifying the economy and reliability of this new hybrid power storage system. The experimental data analysis confirms the practical significance and economic benefits of the proposed scheme in optimizing electric field output. By capitalizing on the strengths of supercapacitors and lithium‐ion batteries, this battery hybrid power storage system provides an efficient and cost‐effective solution for energy storage.

Hybrid electric vehicles (HEVs) represent a significant advancement in automotive technology, bridging the gap between conventional vehicles and pure electric vehicles by combining two distinct power sources. This integration enhances car efficiency and addresses concerns about high fuel consumption and emissions in traditional vehicles. The transition to hybrid models reduces harmful petrol emissions, contributing positively to environmental sustainability and mitigating the impacts of global warming. Machine learning (ML) algorithms play a crucial role in optimizing and assessing the compatibility of typical automobiles with HEVs. Through rigorous testing and refinement, the proposed model exhibits improved accuracy, elevating performance from 81.76% to 86.68%. The incorporation of W‐Saw score and L‐Saw score metrics in an interdisciplinary research methodology further strengthens the optimized model’s reliability and effectiveness. The model’s robustness is evidenced by the high W‐Saw score of 8.8, indicating its strength, and a low L‐Saw Score of 3.3, highlighting minimal errors. The optimized model’s significant W‐Saw score emphasizes its reliability and contribution to environmental sustainability.

With the rapid development of communication technology, from simple communication exchange to today’s perceptual integration, communication systems face many challenges. Among these, hardware impairment (HI) is one of the key factors affecting system performance and reliability, often leading to communication interruptions and signal degradation. To address this challenge, this paper proposes a scheme that combines reconfigurable intelligent surfaces (RIS) and decode‐and‐forward relay (DF) techniques for cooperative transmission in dual slot. In this study, for the case where HI exists at both the receiver and transmitter during signal transmission, multiple RISs are divided into two groups, each participating in signal transmission during one of the two time slots. The outage probability (OP) and throughput of the system are further analyzed by constructing a model of the dual‐slot cooperative communication system and deriving an expression for the overall signal‐to‐interference‐plus‐noise ratio (SINR) of the system over a Nakagami‐m fading channel. Numerical simulation results show that the impact of HIs on the communication system is significant and cannot be ignored. In addition, the scheme in which RISs selectively participate in different time slots shows significant advantages over traditional RIS participation in all reflection schemes. Through numerical simulations, we find that the model can significantly reduce system OP and optimize communication system performance. This finding verifies the effectiveness and superiority of the dual time slot RIS‐DF cooperative communication model under HI conditions.