Abstract This chapter assesses the potential impact of neural networks on package-level failure analysis, the challenges presented by next-generation semiconductor packages, and the measures that can be taken to maximize FA equipment uptime and throughput. It presents examples showing how neural networks have been trained to detect and classify PCB defects, improve signal-to-noise ratios in SEM images, recognize wafer failure patterns, and predict failure modes. It explains how new packaging strategies, particularly stacking and disintegration, complicate fault isolation and evaluates the ability of various imaging methods to locate defects in die stacks. It also presents best practices for sample preparation, inspection, and navigation and offers suggestions for improving the reliability and service life of tools.

Abstract This chapter assesses the potential impact of neural networks on package-level failure analysis, the challenges presented by next-generation semiconductor packages, and the measures that can be taken to maximize FA equipment uptime and throughput. It presents examples showing how neural networks have been trained to detect and classify PCB defects, improve signal-to-noise ratios in SEM images, recognize wafer failure patterns, and predict failure modes. It explains how new packaging strategies, particularly stacking and disintegration, complicate fault isolation and evaluates the ability of various imaging methods to locate defects in die stacks. It also presents best practices for sample preparation, inspection, and navigation and offers suggestions for improving the reliability and service life of tools.

The post-quantum digital signature scheme CRYSTALS-Dilithium has been recently selected by the NIST for standardization. Implementing CRYSTALSDilithium, and other post-quantum cryptography schemes, on embedded devices raises a new set of challenges, including ones related to performance in terms of speed and memory requirements, but also related to side-channel and fault injection attacks security. In this work, we investigated the latter and describe a differential fault attack on the randomized and deterministic versions of CRYSTALS-Dilithium. Notably, the attack requires a few instructions skips and is able to reduce the MLWE problem that Dilithium is based on to a smaller RLWE problem which can be practically solved with lattice reduction techniques. Accordingly, we demonstrated key recoveries using hints extracted on the secret keys from the same faulted signatures using the LWE with side-information framework introduced by Dachman-Soled et al. at CRYPTO’20. As a final contribution, we proposed algorithmic countermeasures against this attack and in particular showed that the second one can be parameterized to only induce a negligible overhead over the signature generation.

We have proposed a combination of large diameter GaN‐on‐Si epiwafers and the usage of existing silicon fab equipment and processes as the ultimate solution to overcome the current cost and yield issues in micro LED display fabrication. In order to utilize the maximum benefits from such combination, in particular for the most advanced 300 mm fabs, it is crucial for the micro LED epiwafers to meet the acceptance criteria of such silicon fabs. An example for a crucial acceptance criteria is the non‐standard thickness substrates which are conventionally used to compensate for the inherent strain‐engineering issues in GaN‐on‐Si epi growth. But for 300 mm silicon fabs the standard thickness of 775 μm needs to be met. In this article, we report how ALLOS manages to achieve the crucial acceptance criteria with its 300 mm GaN‐on‐Si micro LED epiwafers.

Automobiles have witnessed rapid proliferation of infotainment, driver assistance and autonomous driving features which have led to significant increase in semiconductor content per car. However, this has also required increased integration of device functionality to meet the new automotive requirements for in-vehicle networking, autonomous driving, infotainment, and sensor integration. Advance technology/packages are needed to provide ideal solutions for automotive grade reliability, high electrical performance, and multi-function integration for automotive application processors. To address these requirements, innovative packages including Flip Chip Ball Grid Array (FCBGA) are the potential solutions. In this study FCBGA packages are developed for automotive processor application and qualified for AEC2 qualification tier. To achieve higher performance and reliability, different package substrate materials such as core dielectric and build-up dielectric were evaluated. Mechanical modelling and simulation of package reliability and influence of key material properties such as coefficient of thermal expansion (CTE), modulus of elasticity (E) and glass transition temperature (Tg) was used to provide guidance for the selection of substrate and assembly materials. Developed packages met all the product performance requirements and passed package qual conditions of high temperature storage life (150°C, 500 hours), temperature cycling (-55 °C to 125 °C, 1000 cycles), temperature humidity bias (85 °C, 85% RH, 1000 hours) and board level temperature cycling (-40 °C to 125 °C, 1000 cycles).