ZnO Nanowire Field Effect Transistors Research Articles

Passivation effects on ZnO nanowire field effect transistors under oxygen, ambient, and vacuum environments

We investigated the passivation effects on the electrical characteristics of ZnO nanowire field effect transistors (FETs) under the various oxygen environments of ambient air, dry O2, and vacuum. When the ZnO nanowire FET was exposed to more oxygen, the current decreased and the threshold voltage shifted to the positive gate bias direction, due to electrons trapping to the oxygen molecules at the nanowire surface. On the contrary, the electrical properties of the nanowire FET remained unchanged under different environments with passivation by a polymethyl methacrylate layer, which demonstrates the importance of surface passivation for ZnO nanowire-based electronic device applications.

Effect of gate bias sweep rate on the electronic properties of ZnO nanowire field-effect transistors under different environments

We report the effects of gate bias sweep rate on the electronic characteristics of ZnO nanowire field-effect transistors (FETs) under different environments. As the device was swept at slower gate bias sweep rates, the current decreased and threshold voltage shifted to a positive gate bias direction. These phenomena are attributed to increased adsorption of oxygen on the nanowire surface by the longer gate biasing time. Adsorbed oxygens capture electrons and cause a surface depletion in the nanowire channel. Different electrical trends were observed for ZnO nanowire FETs under different oxygen environments of ambient air, N2, and passivation.

Dielectrophoresis (DEP)-prepared multiple-channel ZnO nanowire field-effect transistors

Straightforward and successful dielectrophoresis (DEP)-prepared multiple-channel ZnO nanowire field-effect transistors (FETs) are reported, in which the DEP is used to align and manipulate ZnO nanowires. The DEP-prepared multi-channel ZnO nanowire FETs can manage on-current exceeding ∼1 µA at low bias voltages.

NOT and NAND logic circuits composed of top-gate ZnO nanowire field-effect transistors withhigh-k Al2O3 gate layers

Electrical characteristics of NOT and NAND logic circuits fabricatedusing top-gate ZnO nanowire field-effect transistors (FETs) withhigh-k Al2O3 gate layers were investigated in this study. To form a NOT logic circuit, two identical FETs whoseIon/Ioff ratios wereas high as ∼108 were connected in series in a single ZnO nanowire channel, sharing a common sourceelectrode. Its voltage transfer characteristics exhibited an inverting operation and its logicswing was 98%. In addition, the characteristics of a NAND logic circuit composed of threetop-gate FETs connected in series in a single nanowire channel are discussed in this paper.

Tunable Electronic Transport Characteristics of Surface-Architecture-Controlled ZnO Nanowire Field Effect Transistors

Surface-architecture-controlled ZnO nanowires were grown using a vapor transport method on various ZnO buffer film coated c-plane sapphire substrates with or without Au catalysts. The ZnO nanowires that were grown showed two different types of geometric properties: corrugated ZnO nanowires having a relatively smaller diameter and a strong deep-level emission photoluminescence (PL) peak and smooth ZnO nanowires having a relatively larger diameter and a weak deep-level emission PL peak. The surface morphology and size-dependent tunable electronic transport properties of the ZnO nanowires were characterized using a nanowire field effect transistor (FET) device structure. The FETs made from smooth ZnO nanowires with a larger diameter exhibited negative threshold voltages, indicating n-channel depletion-mode behavior, whereas those made from corrugated ZnO nanowires with a smaller diameter had positive threshold voltages, indicating n-channel enhancement-mode behavior.

Effects of surface roughness on the electrical characteristics of ZnO nanowire field effect transistors

We have systematically investigated the effects of surface roughness on the electrical characteristics of ZnO nanowire field effect transistors (FETs) before and after passivation by poly (methyl metahacrylate) (PMMA), a polymer-insulating layer. To control the surface morphology of ZnO nanowires, ZnO nanowires were grown by the vapor transport method on two different substrates, namely, an Au-catalyzed sapphire and an Au-catalyzed ZnO film/sapphire. ZnO nanowires grown on the Au-catalyzed sapphire substrate had smooth surfaces, whereas those grown on the Au-catalyzed ZnO film had rough surfaces. Electrical characteristics such as the threshold voltage shift and transconductance before and after passivation were strongly affected by the surface morphology of ZnO nanowires.

Multiple ZnO Nanowires Field-Effect Transistors

We report on the multiple ZnO nanowires field-effect transistors (FETs), which were formed by assembling as-synthesized ZnO nanowires on a SiO2/Si substrate using an optimized alternating current (AC) dielectrophoresis (DEP) technique in three-probe back-gate geometry. The AC DEP was optimized with a bias voltage of 10 Vp-p at a frequency of 10 kHz. Our multiple ZnO nanowires FETs containing ca. 50∼65 nanowires in one device exhibited excellent electrical characteristics with a transconductance of 3∼11.5 μS at a drain voltage of 1∼5 V, a mobility of ∼30 cm2/V·s, and a carrier concentration of 9.4 × 1017 cm-3. For a comparison study, we also present conventional single ZnO nanowire FETs prepared by e-beam lithography with a back-gate structure.

Noise properties of a single ZnO nanowire device

ABSTRACTThe low frequency noise of individual ZnO nanowire (NW) field effect transistors (FETs) exposed to air is systematically characterized. The measured noise power spectrum shows a classical 1/f type. The noise amplitude is independent of source-drain current and inversely proportional to gate voltage. The extracted Hooge's constant of ZnO NW is found to be 6.52×10−3. In addition, the low frequency noise of ZnO NW according to NW resistance and contact property are investigated. The noise amplitude is proportional to the square of ZnO NW resistance. If a sample shows a nonlinear current-voltage (I-V) characteristic due to a poor electrical contact, the noise power spectrum is proportional to the third power of current instead of the square of current.

Gas Molecular Adsorption and Surface Cleansing Effects on the Electrical Properties in ZnO Nanowire Field Effect Transistors

Gas Molecular Adsorption and Surface Cleansing Effects on the Electrical Properties in ZnO Nanowire Field Effect Transistors

Fabrication and Characterization of Directly-Assembled ZnO Nanowire Field Effect Transistors with Polymer Gate Dielectrics

We report the fabrication and electrical characterization of ZnO nanowire field effect transistors (FETs). Dielectrophoresis technique was used to directly align ZnO nanowires between lithographically prepatterned source and drain electrodes, and spin-coated polyvinylphenol (PVP) polymer thin layer was used as a gate dielectric layer in "top-gate" FET device configuration. The electrical characteristics of the top-gate ZnO nanowire FETs were found to be comparable to the conventional "bottom-gate" nanowire FETs with a SiO2 gate dielectric layer, suggesting the directly-assembled nanowire FET with a polymer gate dielectric layer is a useful device structure of nanowire FETs.

Fabrication and Characterization of Directly-Assembled ZnO Nanowire Field Effect Transistors with Polymer Gate Dielectrics

We report the fabrication and electrical characterization of ZnO nanowire field effect transistors (FETs). Dielectrophoresis technique was used to directly align ZnO nanowires between lithographically prepatterned source and drain electrodes, and spin-coated polyvinylphenol (PVP) polymer thin layer was used as a gate dielectric layer in "top-gate" FET device configuration. The electrical characteristics of the top-gate ZnO nanowire FETs were found to be comparable to the conventional "bottom-gate" nanowire FETs with a SiO2 gate dielectric layer, suggesting the directly-assembled nanowire FET with a polymer gate dielectric layer is a useful device structure of nanowire FETs.

Electrical Characteristics of ZnO Nanowire-Based Field-Effect Transistors on Flexible Plastic Substrates

ZnO nanowire field effect transistors were fabricated on flexible substrates of poly(ether sulfone) (PES) by bottom-up and photolithographic processes and their electrical characteristics were investigated. The fabrication of the flexible devices was achieved at a processing temperature of 150 °C. A representative top-gate ZnO nanowire field effect transistor (FET) on a flexible substrate exhibits a peak transconductance of 179 nS, a field effect mobility of 10.7 cm2 V-1 s-1, and an Ion/Ioff ratio of 106. When the PES substrate is bent under a strain of 0.77%, the decrement of the drain current for the FET at VGS=10 V is less than 3%.

Enhanced Performance of ZnO Nanowire Field Effect Transistors by H2 Annealing

The electrical properties of ZnO nanowires are significantly dependent on their surface states. The surface trap charges degrade the device performance of field effect transistors. These trap charges are reduced by H2 annealing. In this work, a back-gate ZnO nanowire field effect transistor (FET) was fabricated by a photolithographic process, and its electrical properties were characterized. This back-gate FET was subsequently annealed under a flow of H2/Ar gas for 20 min. The back-gate FET annealed for 20 min exhibited remarkably enhanced electrical characteristics, as compared with the as-fabricated back-gate FET; the peak transconductance was increased from 40 to 448 nS, the field effect mobility from 27 to 302 cm2 V-1 s-1, and the Imax/Imin ratio from 1.5 to 105.

Realization of highly reproducible ZnO nanowire field effect transistors with n-channel depletion and enhancement modes

The authors demonstrate the highly reproducible fabrication of n-channel depletion-mode (D-mode) and enhancement-mode (E-mode) field effect transistors (FETs) created from ZnO nanowires (NWs). ZnO NWs were grown by the vapor transport method on two different types of substrates. It was determined that the FETs created from ZnO NWs grown on an Au-coated sapphire substrate exhibited an n-channel D mode, whereas the FETs of ZnO NWs grown on an Au-catalyst-free ZnO film exhibited an n-channel E mode. This controlled fabrication of the two operation modes of ZnO NW-FETs is important for the wide application of NW-FETs in logic circuits.

Electrical properties of ZnO nanowire field effect transistors by surface passivation

We have synthesized single crystalline ZnO nanowires by thermal evaporation method and fabricated individual ZnO nanowire field effect transistors (FETs) to investigate their electrical properties. ZnO nanowires are strongly affected by O2 molecules in ambient. For example, surface defects such as oxygen vacancies act as adsorption sites of O2 molecules, and the chemisorption of O2 molecules depletes the surface electron states and reduces the channel conductivity. Therefore, it is important to protect the electrical properties of ZnO nanowires by surface passivation. For this purpose, we investigated the changes of the electrical properties of ZnO nanowire FETs with and without passivation by an organic material, poly(methyl metahacrylate) (PMMA). The ZnO nanowire FETs with PMMA passivation exhibited better performance in comparison with unpassivated devices.

High performance ZnO nanowire field effect transistors with organic gate nanodielectrics:effects of metal contacts and ozone treatment

High performance ZnO nanowire field effect transistors (NW-FETs) were fabricated using ananoscopic self-assembled organic gate insulator and characterized in terms of conventionaldevice performance metrics. To optimize device performance and understand the effects ofinterface properties, devices were fabricated with both Al and Au/Ti source/drain contacts,and device electrical properties were characterized following annealing and ozonetreatment. Ozone-treated single ZnO NW-FETs with Al contacts exhibited an on-current(Ion) of∼4 µA at0.9 Vgs and1.0 Vds, a thresholdvoltage (Vth) of 0.2 V, asubthreshold slope (S) of ∼130 mV/decade, an on–offcurrent ratio (Ion:Ioff)of ∼107, and a fieldeffect mobility (μeff) of ∼1175 cm2 V−1 s−1.In addition, ozone-treated ZnO NW-FETs consistently retained the enhanced device performance metricsafter SiO2 passivation. A 2D device simulation was performed to explain the enhanced deviceperformance in terms of changes in interfacial trap and fixed charge densities.

Low frequency noise characterizations of ZnO nanowire field effect transistors

We fabricated ZnO nanowire field effect transistors (FETs) and systematically characterized their low frequency (f) noise properties. The obtained noise power spectra showed a classical 1∕f dependence. A Hooge’s constant of 5×10−3 was estimated from the gate dependence of the noise amplitude. This value is within the range reported for complementary metal-oxide semiconductor (CMOS) FETs with high-k dielectrics, supporting the concept that nanowires can be utilized for future beyond-CMOS electronic applications from the point of view of device noise properties. ZnO FETs measured in a dry O2 environment displayed elevated noise levels that can be attributed to increased fluctuations associated with O2− on the nanowire surfaces.

A fabrication technique for top-gate ZnO nanowire field-effect transistors by a photolithography process

In this study, top-gate ZnO nanowire field-effect transistors (FETs) were successfully fabricated using a photolithography process, and their electrical properties were characterized by I–V measurements. Their electrical characteristics were compared with those of back-gate ZnO nanowire FETs. The fabricated nanowire FETs exhibit good contact between the ZnO nanowire channels and Ti metal electrodes. A representative top-gate FET showed a higher gate dependence than a representative back-gate FET; the peak transconductances of the back- and top-gate FETs were 19 nS and 248 nS, respectively. These characteristics reveal that the top-gate nanowire FET fabricated by the photolithography process has better performance. The fabrication technique used for the nanowire FETs by a photolithography process in this study is applicable to the fabrication of various devices including TFTs, memory devices, photodetectors, and so on.

Role of grain boundaries in ZnO nanowire field-effect transistors

ZnO nanowires have attracted strong interest for potential nanoelectronics, optoelectronics, and nanosensor applications. The role of grain boundaries (GBs) in ZnO nanowire transistors is examined by solving a two-dimensional Schrödinger equation in the nanowire cross section, coupled to a drift-diffusion equation along the nanowire. We show that a GB results in a potential barrier with the thickness determined by the gate insulator thickness and the height determined by the number of the trap states at the GB. The GB leads to a decrease of the source-drain current because the voltage drop at the GB reduces the electric field at other channel positions. The on current depends on the nanowire diameter nonmonotonically due to two competing mechanisms. Increasing the number of GBs in the channel decreases both the on current and off current. When the total number of GBs is small, its effect on the I-V characteristics can be phenomenologically viewed as an increase of the threshold voltage. When the total number of GBs is larger, it must be viewed as a combined effect of the increase of the threshold voltage and the decrease of the channel effective mobility.

High performance ZnO nanowire field effect transistor using self-aligned nanogap gate electrodes

A field effect transistor (FET) using a zinc oxide nanowire with significantly enhanced performance is demonstrated. The device consists of single nanowire and self-aligned gate electrodes with well defined nanosize gaps separating them from the suspended nanowire. The fabricated FET exhibits excellent performance with a transconductance of 3.06μS, a field effect mobility of 928cm2∕Vs, and an on/off current ratio of 106. The electrical characteristics are the best obtained to date for a ZnO transistor. The FET has a n-type channel and operates in enhancement mode. The results are close to those reported previously for p-type carbon nanotube (CNT) FETs. This raises the possibility of using ZnO as the n-type FET with a CNT as the p-type FET in nanoscale complementary logic circuits.