Worst-case Time Analysis Research Articles

The Mixed Binary Euclid Algorithm

We present a new GCD algorithm for two integers that combines both the Euclidean and the binary gcd approaches. We give its worst case time analysis and we prove that its bit-time complexity is still O(n 2 ) for two n-bit integers in the worst case. Our preliminar experiments show a potential speedup for small integers. A parallel version matches the best presently known time complexity, namely O(n/ log n )t ime with O(n 1+� ) processors, for any constant �> 0.

A measure & conquer approach for the analysis of exact algorithms

For more than 40 years, Branch & Reduce exponential-time backtracking algorithms have been among the most common tools used for finding exact solutions of NP-hard problems. Despite that, the way to analyze such recursive algorithms is still far from producing tight worst-case running time bounds. Motivated by this, we use an approach, that we call “Measure & Conquer”, as an attempt to step beyond such limitations. The approach is based on the careful design of a nonstandard measure of the subproblem size; this measure is then used to lower bound the progress made by the algorithm at each branching step. The idea is that a smarter measure may capture behaviors of the algorithm that a standard measure might not be able to exploit, and hence lead to a significantly better worst-case time analysis. In order to show the potentialities of Measure & Conquer, we consider two well-studied NP-hard problems: minimum dominating set and maximum independent set. For the first problem, we consider the current best algorithm, and prove (thanks to a better measure) a much tighter running time bound for it. For the second problem, we describe a new, simple algorithm, and show that its running time is competitive with the current best time bounds, achieved with far more complicated algorithms (and standard analysis). Our examples show that a good choice of the measure, made in the very first stages of exact algorithms design, can have a tremendous impact on the running time bounds achievable.

Formula omitted]; unlocking the potential of compositional static average-case analysis

Compositionality is the “golden key” to static analysis and plays a central role in static worst-case time analysis. We show that compositionality, combined with the capacity for tracking data distributions, unlocks a useful novel technique for average-case analysis.The applicability of the technique has been demonstrated via the static average-case analysis tool DISTRI. The tool automatically extracts average-case time from source code of programs implemented in the novel programming language MOQA1MOdular Quantitative Analysis.1. MOQA enables the prediction of the average number of basic steps performed in a computation, paving the way for static analysis of complexity measures such as average time or average power use. MOQA has as a unique feature a guaranteed average-case timing compositionality.The compositionality property brings a strong advantage for the programmer. The capacity to combine parts of code, where the average-time is simply the sum of the times of the parts, is a very helpful advantage in static analysis, something which is not available in current languages. Moreover, re-use is a key factor in the MOQA approach: once the average time is determined for a piece of code, then this time will hold in any context. Hence it can be re-used and the timing impact is always the same. Compositionality also improves precision of static average-case analysis, supporting the determination of accurate estimates on the average number of basic operations of MOQA programs.The MOQA “language” essentially consists of a suite of data-structuring operations together with conditionals, for-loops and recursion. As such MOQA can be incorporated in any traditional programming language, importing all of its benefits in a familiar context2MOQA is implemented at CEOL in Java 5.0 as MOQA-java.2.Compositionality for average-case is subtle and one may easily be tempted to conclude that compositionality “comes for free”. For genuine compositional reasoning however, one needs to be able to track data and their distribution throughout computations; a non-trivial problem. The lack of an efficient method to track distributions has plagued all prior static average-case analysis approaches. We show how MOQA enables the finitary representation and tracking of the distribution of data states throughout computations. This enables one to unlock the true potential of compositional reasoning. Links with reversible computing are discussed. The highly visual aspect of this novel and unified approach to the Analysis of Algorithms also has a pedagogical advantage, providing students with useful insights in the nature of algorithms and their analysis.

Pathwidth of cubic graphs and exact algorithms

We prove that for any ɛ > 0 there exists an integer n ɛ such that the pathwidth of every cubic (or 3-regular) graph on n > n ɛ vertices is at most ( 1 / 6 + ɛ ) n . Based on this bound we improve the worst case time analysis for a number of exact exponential algorithms on graphs of maximum vertex degree three.

THE INFLUENCE OF INTER-DOMAIN MOBILITY ON MESSAGE STREAM RESPONSE TIME IN WIRED/WIRELESS PROFIBUS-BASED NETWORKS

In previous works we have proposed a hybrid wired/wireless PROFIBUS solution where the interconnection between the heterogeneous media was accomplished through bridge-like devices with wireless stations being able to move between different wireless cells. Additionally, we had also proposed a worst-case timing analysis assuming that stations were stationary. In this paper we advance these previous works by proposing a worst-case timing analysis for the system's message streams considering the effect of inter-cell mobility.

Flattening statecharts without explosions

We present a polynomial upper bound for flattening of UML statecharts. An efficient flattening technique is derived and implemented in SCOPE---a code generator targeting constrained embedded systems. Programs generated with this new technique are both faster and smaller than those produced by non-flattening code generators. Our approach scales well for big models and exhibits good properties with respect to memory usage, automatic analysis of worst-case reaction time and automatic validation of memory safety.

Virtual simple architecture (VISA)

Meeting deadlines is a key requirement in safe realtime systems. Worst-case execution times (WCET) of tasks are needed for safe planning. Contemporary worst-case timing analysis tools can safely and tightly bound execution time on in-order single-issue pipelines with caches and static branch prediction. However, this simple pipeline appears to be a complexity limit, due to the need for analyzability. This excludes a whole class of high-performance processors from many embedded systems.We reconcile the complexity/safety trade-off by decoupling worst-case timing analysis from the processor implementation, through a virtual simple architecture (VISA). A VISA is the timing specification of a hypothetical simple pipeline and is the basis for worst-case timing analysis. However, the underlying microarchitecture can be arbitrarily complex. A task is divided into multiple sub-tasks which provide a means to gauge progress on the complex pipeline. Each sub-task is assigned an interim deadline, or checkpoint, based on the latest allowable completion time of the sub-task on the hypothetical simple pipeline. If no checkpoints are missed, then the complex pipeline is as timely as the safe pipeline. If a checkpoint is missed, the pipeline switches to a simple mode of operation that directly implements the VISA so that execution time of unfinished sub-tasks is safely bounded. The significance of our approach is that we circumvent worst-case timing analysis of the complex pipeline, by dynamically confirming its behavior is bounded by worst-case timing analysis of a simpler proxy pipeline.The benefit of using a high-performance processor is that tasks finish much sooner than they would have on an explicitly-safe processor. The new slack in the schedule can be exploited for higher throughput or lower power. With the VISA approach, an arbitrarily complex SMT processor can safely run non-real-time tasks at the same time as a real-time task. Alternatively, frequency/voltage can be safely lowered to take up slack. We explore the latter application and show a VISA-compliant complex pipeline consumes 43--61% less power than an explicitly-safe pipeline.

Timing Analysis for Data and Wrap-Around Fill Caches

The contributions of this paper are twofold. First, an automatic tool-based approach is described to bound worst-case data cache performance. The approach works on fully optimized code, performs the analysis over the entire control flow of a program, detects and exploits both spatial and temporal locality within data references, and produces results typically within a few seconds. Results obtained by running the system on representative programs are presented and indicate that timing analysis of data cache behavior usually results in significantly tighter worst-case performance predictions. Second, a method to deal with realistic cache filling approaches, namely wrap-around-filling for cache misses, is presented as an extension to pipeline analysis. Results indicate that worst-case timing predictions become significantly tighter when wrap-around-fill analysis is performed. Overall, the contribution of this paper is a comprehensive report on methods and results of worst-case timing analysis for data caches and wrap-around caches. The approach taken is unique and provides a considerable step toward realistic worst-case execution time prediction of contemporary architectures and its use in schedulability analysis for hard real-time systems.

Combining static worst-case timing analysis and program proof

This paper describes SPATS—a new toolset for the development of safety-critical and hard real-time systems. SPATS integrates the analysis traditionally offered by program proof and static timing analysis tools through analysis of program basic-path graphs. This paper concentrates on SPATS' facilities for high-level static timing analysis and analysis of worst-case stack usage. The integration of timing analysis and program proof allows timing analysis to be performed where worst-case execution time (WCET) depends on a program's input data, and allows timing annotations to be formally verified. The approach is developed and illustrated with a worked example. The implementation and experimental application of SPATS to realistic industrial case-studies are also described. We conclude that SPATS offers a novel new approach to static timing analysis, offers several new analyses not seen in previous systems, and can be implemented in a useful and efficient toolset.

Temporal constraint reasoning mechanisms for microprocessor systems diagnosis

Abstract A diagnostic system for microprocessor systems design is being designed and developed. In microprocessor systems diagnosis and design, temporal reasoning about event changes occurring at imprecisely knon time instants is an important issue. The concept of a time range has been proposed to capture the notion of time imprecision in event occurrence. According to this concept, efficient temporal reasoning techniques for constraint satisfaction and propagation of time ranges have been developed for the embedding of domain knowledge in a deep-level constraint model. The imprecision in these events contributes to a certain degree of uncertainty about the correctness of a microprocessor system operation. The proposed system performs worst-case timing analysis. In particular, for the asynchronous bus operation of the MC68000 microprocessor, the sequence of events during a read cycle is traced through an inference process to determine whether any constraint in the model is violated. Satisfactory results have been obtained in a practical implementation of the system using the CLIPS expert system shell.

An accurate worst case timing analysis for RISC processors

An accurate and safe estimation of a task's worst case execution time (WCET) is crucial for reasoning about the timing properties of real time systems. In RISC processors, the execution time of a program construct (e.g., a statement) is affected by various factors such as cache hits/misses and pipeline hazards, and these factors impose serious problems in analyzing the WCETs of tasks. To analyze the timing effects of RISC's pipelined execution and cache memory, we propose extensions to the original timing schema where the timing information associated with each program construct is a simple time bound. In our approach, associated with each program construct is worst case timing abstraction, (WCTA), which contains detailed timing information of every execution path that might be the worst case execution path of the program construct. This extension leads to a revised timing schema that is similar to the original timing schema except that concatenation and pruning operations on WCTAs are newly defined to replace the add and max operations on time bounds in the original timing schema. Our revised timing schema accurately accounts for the timing effects of pipelined execution and cache memory not only within but also across program constructs. The paper also reports on preliminary results of WCET analysis for a RISC processor. Our results show that tight WCET bounds (within a maximum of about 30% overestimation) can be obtained by using the revised timing schema approach. >

A worst case timing analysis technique for instruction prefetch buffers

Predictable performance is crucial for real-time computing systems. We propose a buffered threaded prefetch scheme as a predictable and high performance instruction memory hierarchy. We also give extensions to the timing schema[3] to analyze the timing effects of the proposed scheme. In the extended timing schema, we associate with each program construct what we call a WCTA (Worst Case Timing Abstraction), which contains detailed timing information of the program construct. By defining a concatenation operation on WCTAs, our revised timing schema accurately accounts for the timing effects of the buffered threaded prefetching not only within but also across program constructs. This paper shows, through analysis using a timing tool based on the extended timing schema, the buffered prefetch scheme significantly improves the worst case execution times of tasks.

Static worst-case timing analysis of Ada

This paper describes recent work on static timing analysis of Ada. Previous work on static timing analysis has not considered Ada, so one goal of this paper is to raise awareness of the topic within the Ada community. We believe the technology is now sufficiently well-understood that commercial tools for a small subset are within reach. We first consider timing analysis in general, and then look at the particular features of Ada in this light. The technical detail of one recently developed tool is then covered. Finally, we consider the impact of Ada9X and some open issues raised by our research.

Probability based timing verification

Worst case timing analysis is the well ~nown method of making sure that the device will operate after assembly. Unfortunately it results in ca SOZ lower performance than ultimately needed. The statistical methods for design verification [i] are extremely timeconsuming especially for the systems with considerable complexity, Nevertheless they are used because design quality appeared to be one of the Key issues in computer hardware design lately. The probability based timing verification is meant actually for the same tasK, but needs significantly less computing power, It is also a method of predicting indirectly the yield of digital systems (IC-S). The pioneer in this area is, no doubt, B. Magnnagen [2] whose algoritllms are implemented in DIGSIM and DIXI-cad systems. The proDabilistic timing verification is based on the time variables of the schematics elements. These variables are distributed in some way around the mean value, commonly specified as typical on the element data sheet. From the typical and min or max values the mean square deviation can De estimated, with each transition on the signal the mean time of occurrence and the standard deviation are associated, The time characteristics of the transition (t,o) on the signal usually are computed according to the well Known formulas, using the mean delays of elements t i, i:I,2 . . . . . K and their standard devzations on the signal propagation path 0 i, i:i,2, .... ~.

On a proposed divide-and-conquer minimal spanning tree algorithm

In a recent paper published in this journal, R. Chang and R. Lee purport to devise anO(N logN) time minimal spanning tree algorithm forN points in the plane that is based on a divide-and-conquer strategy using Voronoi diagrams. In this brief note, we present families of problem instances to show that the Chang-Lee worst-case timing analysis is incorrect, resulting in a time bound ofO(N2 logN). Since it is known that alternate, trulyO(N logN) time algorithms are available anyway, the general utility of the Chang-Lee algorithm is questionable.