Worst-case Time Analysis Research Articles

Worst-Case Communication Time Analysis for On-Chip Networks With Finite Buffers

Network-on-Chip (NoC) is the ideal interconnection architecture for many-core systems due to its superior scalability and performance. An NoC must deliver critical messages from a real-time application within specific deadlines. A violation of this requirement may compromise the entire system operation. Therefore, a series of experiments considering worst-case scenarios must be conducted to verify if deadlines can be satisfied. However, simulation-based experiments are time-consuming, and one alternative is schedulability analysis. In this context, this work proposes a schedulability analysis to accelerate design space exploration in real-time applications on NoC-based systems. The proposed worst-case analysis estimates the maximum latency of traffic flows assuming direct and indirect blocking. Besides, we consider the size of buffers to reduce the analysis’ pessimism. We also present an extension of the analysis, including self-blocking. We conduct a series of experiments to evaluate the proposed analysis using a cycle-accurate simulator. The experimental results show that the proposed solution presents tighter results and runs four orders of magnitude faster than the simulation.

Worst-Case Delay Bounds in Time-Sensitive Networks With Packet Replication and Elimination

Packet replication and elimination functions are used by time-sensitive networks (as in the context of IEEE TSN and IETF DetNet) to increase the reliability of the network. Packets are replicated onto redundant paths by a replication function. Later the paths merge again and an elimination function removes the duplicates. This redundancy scheme has an effect on the timing behavior of time-sensitive networks and many challenges arise from conducting timing analyses. The replication can induce a burstiness increase along the paths of replicates, as well as packet mis-ordering that could increase the delays in the crossed bridges or routers. The induced packet mis-ordering could also negatively affect the interactions between the redundancy and scheduling mechanisms such as traffic regulators (as with per-flow regulators and interleaved regulators, implemented by TSN asynchronous traffic shaping). Using the network calculus framework, we provide a method of worst-case timing analysis for time-sensitive networks that implement redundancy mechanisms in the general use case, i.e., at end-devices and/or intermediate nodes. We first provide a network calculus toolbox for bounding the burstiness increase and the amount of reordering caused by the elimination function of duplicate packets. We then analyze the interactions with traffic regulators and show that their shaping-for-free property does not hold when placed after a packet elimination function. We provide a bound for the delay penalty when using per-flow regulators and prove that the penalty is not bounded with interleaved regulators. Finally, we use an industrial use-case to show the applicability and the benefits of our findings.

Global Fixed-Priority Scheduling for Parallel Real-Time Tasks with Constrained Parallelism

With the rapid development of parallel programming techniques and the widespread use of multiprocessors, scheduling and analysis techniques supporting parallel real-time tasks become a critical topic for multiprocessor real-time systems. Global scheduling that allows the vertices of a parallel task to execute on any processor is a promising scheduling approach with guaranteed theoretical bounds and wide use in practice. However, the complex internal structure of parallel tasks leads to extensive inner- and inter-task interference, which leads to significant pessimism in the worst-case timing analysis. In this paper, a global fixed-priority (G-FP) scheduling with constrained parallelism for parallel real-time tasks based on the sporadic directed acyclic graph (DAG) model is proposed. Each DAG task is assigned a parallel threshold, such that the number of processors occupied by the task is limited to the parallel threshold of the task at a time. We propose a heuristic algorithm to set the parallel threshold and present a response-time analysis (RTA) to exploit the feature of the constrained parallel scheduling. Experiments with randomly generated tasks show that the proposed approach improves the schedulability upon G-FP and federated scheduling in terms of acceptance ratio.

Worst-case traversal time analysis of TSN with multi-level preemption

Abstract To achieve low latency transmission of time-sensitive flows in Ethernet networks, the IEEE introduced the IEEE 802.1Qbu Standard, which specifies a 1-level preemption scheme for IEEE 802.1 networks. The specification allows the suspension of a preemptable frame prior to its completion for the speedy transmission of an express frame; but any other preemptable frame cannot be transmitted before the completion of the already preempted frame. While this approach improves the performance of express frames, the performance is negatively impacted in scenarios where the number of express frames is high. Another limitation is the fact that preemptable frames with timing requirements can suffer long blocking periods due to the non-preemptive service of frames in the same category. This is irrespective of the individual priority level of each frame. Recently, a multi-level preemption scheme has been proposed to circumvent these limitations. The work focused on the feasibility and implementation requirement of such an approach, but a formal analysis of the worst-case performance guarantees under the proposed scheme was not provided. In this paper, we fill this gap by presenting the aforementioned analysis of the TSN IEEE 802.1Qbu networks under the multi-level preemption assumption. Evaluation is performed with a realistic automotive use-case and the results showcase an improvement up to 53.07% for preemptable frames with firm timing requirements.

Optimization-Time Analysis for Cybersecurity

A mathematical framework to reason about time resilience in cybersecurity is here introduced. We first consider an attacker who is able to mount several multi-stage attacks on the organization: the defender’s objective is to select an optimal portfolio of security controls, within a given budget, to withstand the highest number of attacks. The mathematical model is a Markov chain with an initial state called the safe state, intermediate states for all possible attacks (each attack state denoting a probabilistic attack graph), and a sink state denoting a successful attack. The overall defence problem is formulated as a bi-level multi-objective optimization, i.e., the defender selects an optimal portfolio of security controls to mitigate an optimal attacker. In order to determine the probability of success of an attack two cases will be considered: (a) the expected probability of success and (b) the highest probability of success. We refer to these two cases as expected-time analysis and worst-case time analysis, respectively. To solve precisely these bi-level optimizations strong duality and Mixed Integer Linear Programming are used. We then extend the framework to investigate resilience in terms of the total duration of the attacks; variations of the previous optimizations are presented to this purpose. Finally numerical evaluations are provided to compare the results obtained from the expected-time analysis and the worst-case time analysis.

An Adaptive Version of Brandes' Algorithm for Betweenness Centrality

Betweenness centrality-measuring how many shortest paths pass through a vertex-is one of the most important network analysis concepts for assessing the relative importance of a vertex. The well-known algorithm of Brandes [J. Math. Sociol. '01] computes, on an $n$-vertex and $m$-edge graph, the betweenness centrality of all vertices in $O(nm)$ worst-case time. In later work, significant empirical speedups were achieved by preprocessing degree-one vertices and by graph partitioning based on cut vertices. We contribute an algorithmic treatment of degree-two vertices, which turns out to be much richer in mathematical structure than the case of degree-one vertices. Based on these three algorithmic ingredients, we provide a strengthened worst-case running time analysis for betweenness centrality algorithms. More specifically, we prove an adaptive running time bound $O(kn)$, where $k < m$ is the size of a minimum feedback edge set of the input graph.

Graph-Based Approach for Buffer-Aware Timing Analysis of Heterogeneous Wormhole NoCs Under Bursty Traffic

This paper addresses the problem of worst-case timing analysis of heterogeneous wormhole NoCs, i.e., routers with different buffer sizes and transmission speeds, when consecutive-packet queuing (CPQ) occurs. The latter means that there are several consecutive packets of one flow queuing in the network. This scenario happens in the case of bursty traffic but also for non-schedulable traffic. Conducting such an analysis is known to be a challenging issue due to the sophisticated congestion patterns when enabling backpressure mechanisms. We tackle this problem through extending the applicability domain of our previous work for computing maximum delay bounds using Network Calculus, called Buffer-aware worst-case Timing Analysis (BATA). We propose a new Graph-based approach to improve the analysis of indirect blocking due to backpressure, while capturing the CPQ effect and keeping the information about dependencies between flows. Furthermore, the introduced approach improves the computation of indirect-blocking delay bounds in terms of complexity and ensures the safety of these bounds even for nonschedulable traffic. We provide further insights into the tightness and complexity issues of worst-case delay bounds yielded by the extended BATA with the Graph-based approach, denoted G-BATA. Our assessments show that the complexity has decreased by up to 100 times while offering an average tightness ratio of 71%, with reference to the basic BATA. Finally, we evaluate the yielded improvements with G-BATA for a realistic use case against a recent state-of-the-art approach. This evaluation shows the applicability of GBATA under more general assumptions and the impact of such a feature on the tightness and computation time

Worst-Case Timing Analysis of AFDX Networks With Multiple TSN/BLS Shapers

This paper addresses the problem of worst-case timing analysis of extended Avionics Full Duplex Switched Ethernet (AFDX) networks, incorporating Time-Sensitive Networking (TSN) shapers called Burst Limiting Shapers (BLS), to enable the interconnection of different avionics domains with mixed-criticality levels, e.g., current AFDX traffic, Flight Control and In-Flight Entertainment. Conducting such an analysis is a challenging issue when considering multiple BLS-shaped traffic classes, due to the sophisticated inter-dependencies between the different shapers sharing the same output capacity. We tackle this problem through extending the applicability domain of our previous work for computing maximum delay bounds using Network Calculus and considering only one BLS class, called Continuous Credit-based Approach (CCbA), to handle multiple TSN/BLS classes. We provide further insights into the sensitivity and tightness issues of worst-case delay bounds yielded with the Generalized CCbA (GCCbA). Our assessments show that the tightness ratio is up to 85%, with reference to Achievable Worst-Case delays. We also show the improvements against recent state-of-the-art approaches in terms of tightness and complexity, where the computation time is up to 105 faster. Finally, we evaluate the efficiency of GCCbA for realistic avionics case studies, e.g., adding A350 flight control traffic to the AFDX. Results show the good applicability of GCCbA and confirm the efficiency of the extended AFDX, which decreases the delay bounds of the existing AFDX traffic by up to 49.9%, in comparison with the current AFDX standard.

Challenges and Limitations of IEEE 802.1CB-2017

For many Ethernet-based real-time systems, such as those from automotive, avionics, and industry automation domains, fault tolerance is emerged as an essential requirement for enabling fail-safe or fail-operational behavior. Consequently, the IEEE 802.1CB-2017 standard was published. It is currently the only available time-sensitive networking group standard offering protection against transmission errors. It tackles these faults by preventively replicating the frames and transmitting redundant copies via different paths to the destination. However, in contrast to its obvious advantages, the standard contains some pitfalls: most notably, it lacks protection mechanisms against inadequate configurations, which can not only invalidate the intended increase in reliability but even actively jeopardize the safety of the network. Due to the lack of alternative mechanisms, it is crucial to fully understand the fundamental properties of the standard and its implications on the safety aspects of the network traffic. In this letter, we identify critical aspects and limitations of the standard. We demonstrate the risks of inadequate configurations, discuss their ramifications. Finally, we provide an intuition and initial steps toward deriving the formal worst-case timing analysis of the standard, which is a key requirement for its safe and efficient implementation in the aforementioned real-time domains.

Safe and efficient power management of hard real-time networks-on-chip

The power overhead of Networks-on-Chip (NoCs) becomes tremendous in high density Multiprocessor Systems-on-Chip (MPSoCs). Especially in hard real-time and safety-critical systems, power management mechanisms must be developed and efficiently adhered to real-time requirements. However, state-of-the-art solution typically induces a high timing overhead, thus challenging safety, or has limited power saving capabilities. Additionally, current power-gating mechanisms do not provide an upper bound of the latency overhead, and thus no timing guarantees. We propose a safe and enhanced approach for power-gating that allows a global and dynamic power management under timing guarantees, i.e., all deadlines of critical tasks are met. It introduces a control-layer to save power on the NoC data layer using multiple Power-Aware Traffic-Monitor (PATM) units, which apply knowledge of the global state of the system to efficiently save power on NoC routers even at high NoCs utilizations. To safely apply the PATMs in hard real-time systems while meeting the deadlines, we provide a formal worst-case timing analysis to derive PATMs upper bound latency overhead. Experimental results show that our approach efficiently reduces static power consumption, and provides scalability inducing very small area overhead.

Robust Self-Calibrated Dynamic Voltage Scaling in FPGAs With Thermal and IR-Drop Compensation

Field programmable gate arrays (FPGAs) are widely used in telecom, medical, military, cloud computing, and other high-performance computing applications, thanks to their unique combination of parallel hardware execution and reprogrammability. During compilation, the computer-aided design (CAD) tool estimates the maximum operating frequency of the user application based on the worst case timing analysis of the critical path at a fixed nominal supply voltage, which usually results in significant voltage or frequency margin. Hence dynamic voltage scaling (DVS) has great potential to reduce the power overhead in FPGAs; however, the reprogrammability of FPGAs make a safe implementation of DVS for any application that could be programmed into the FPGA challenging. This work presents a robust universal DVS scheme for FPGAs intended to run on a system production line, or regularly during each FPGA power-up. The proposed scheme requires the FPGA to be programmed twice: offline self-calibration and online DVS. During the offline self-calibration, the FPGA frequency and core voltage operating limits at different self-imposed temperatures are automatically found and stored in a calibration table (CT). During online operation, the power stage refers to the CT and dynamically adjusts the core voltage according to the FPGA temperature and the resistive voltage drop in the power delivery path. The proposed DVS scheme is demonstrated on a 60-nm Intel Cyclone IV FPGA, with a digitally controlled dc–dc converter, leading to 40% power savings in two typical applications.

Extended recursive analysis for tilera tile64 NoC architectures

A heterogeneous network, where a switched-Ethernet backbone, e.g. AFDX, interconnects several end systems based on Network-on-Chip (NoC), is a promising candidate to build new avionics architectures. When using such a heterogeneous network for real-time applications, a global worst-case traversal time (WCTT) analysis is needed. In this short paper we focus on the intra-NoC communication on a Tilera TILE64-like NoC. First, we extend the Recursive Calculus (RC) to achieve tighter intra-NoC WCTT. Then, we explain how this intra-NoC WCTT analysis could be used in a compositional manner for the end-to-end inter-NoC delay analysis.

Isolation scheduling on multicores: model and scheduling approaches

Deploying real-time applications on multicores is challenging because tasks that are executed concurrently on different cores can interfere on shared resources, severely complicating worst-case timing analysis. To tackle this challenge, we propose a new scheduling model called isolation scheduling (IS): IS provides a framework to exploit multicores for real-time applications where tasks are grouped into classes. IS enforces mutually exclusive execution among different task classes, thus eliminating inter-class interference by construction. We assume that interference due to the statefulness of shared resources is either negligible or accounted for in the worst-case execution time of tasks. Mixed-criticality systems provide an example where IS is applicable. We propose and analyze two novel approaches for isolation scheduling: a global approach based on fluid scheduling and a partitioned approach based on hierarchical server scheduling, each with extensions to mixed-criticality applications. Through extensive simulations, we compare the two approaches in terms of schedulability and runtime overheads and quantify the schedulability loss due to the isolation constraint. Moreover, we conduct a comparative study among state-of-the-art approaches that comply with our IS model, showing that the new approaches can significantly outperform existing ones in terms of schedulability.

Evaluation of a low overhead predication system for a deterministic VLIW architecture targeting real-time applications

Recently, there is a considerable research effort on providing time-predictable architectures for real-time systems. The correct functioning of them depends not only on the logically correct response, but also the time when it is given. To provide such determinism, the use of VLIW (Very Long Instruction Word) architecture with in-order pipelines and predication support became attractive. Predication is an architecture technique which helps the compiler to translate control dependencies into data dependencies reducing control flow overhead and enhancing the worst-case timing analysis. Since hardware predication support does not come for free, the goal of this work is to investigate a low overhead predication system for multi-issue VLIW machines targeting real-time applications. This study was conducted using a VLIW 4-issue prototype based on the VLIW HP ST231 ISA describing the hardware implementation and the benefits on the worst-case performance.

Ensuring safety and efficiency in networks-on-chip

Networks-on-Chip (NoCs) for real-time systems require solutions for safe and predictable sharing of network resources between transmissions with different quality of service requirements. In this work, we present a mechanism for a global and dynamic admission control in NoCs dedicated to real-time systems. It introduces an overlay network to synchronize transmissions using arbitration units called Resource Managers (RMs), which allows a global and work-conserving scheduling. We present a formal worst-case timing analysis for the proposed mechanism and demonstrate that this solution not only exposes higher performance in simulation but, even more importantly, consistently reaches smaller formally guaranteed worst-case latencies than TDM for realistic levels of system's utilization. Our mechanism does not require the modification of routers and therefore can be used together with any architecture utilizing non-blocking routers.

Worst-Case Finish Time Analysis for DAG-Based Applications in the Presence of Transient Faults

Tasks in hard real-time systems are required to meet preset deadlines, even in the presence of transient faults, and hence the analysis of worst-case finish time (WCFT) must consider the extra time incurred by re-executing tasks that were faulty. Existing solutions can only estimate WCFT and usually result in significant under- or over-estimation. In this work, we conclude that a sufficient and necessary condition of a task set experiencing its WCFT is that its critical task incurs all expected transient faults. A method is presented to identify the critical task and WCFT in O(|V | + |E|) where |V | and |E| are the number of tasks and dependencies between tasks, respectively. This method finds its application in testing the feasibility of directed acyclic graph (DAG) based task sets scheduled in a wide variety of fault-prone multi-processor systems, where the processors could be either homogeneous or heterogeneous, DVS-capable or DVS-incapable, etc. The common practices, which require the same time complexity as the proposed critical-task method, could either underestimate the worst case by up to 25%, or overestimate by 13%. Based on the proposed critical-task method, a simulated-annealing scheduling algorithm is developed to find the energy efficient fault-tolerant schedule for a given DAG task set. Experimental results show that the proposed critical-task method wins over a common practice by up to 40% in terms of energy saving.

Schedule refinement for homogeneous multi-core processors in the presence of manufacturing-caused heterogeneity

Multi-core homogeneous processors have been widely used to deal with computation-intensive embedded applications. However, with the continuous down scaling of CMOS technology, within-die variations in the manufacturing process lead to a significant spread in the operating speeds of cores within homogeneous multi-core processors. Task scheduling approaches, which do not consider such heterogeneity caused by within-die variations, can lead to an overly pessimistic result in terms of performance. To realize an optimal performance according to the actual maximum clock frequencies at which cores can run, we present a heterogeneity-aware schedule refining (HASR) scheme by fully exploiting the heterogeneities of homogeneous multi-core processors in embedded domains. We analyze and show how the actual maximum frequencies of cores are used to guide the scheduling. In the scheme, representative chip operating points are selected and the corresponding optimal schedules are generated as candidate schedules. During the booting of each chip, according to the actual maximum clock frequencies of cores, one of the candidate schedules is bound to the chip to maximize the performance. A set of applications are designed to evaluate the proposed scheme. Experimental results show that the proposed scheme can improve the performance by an average value of 22.2%, compared with the baseline schedule based on the worst case timing analysis. Compared with the conventional task scheduling approach based on the actual maximum clock frequencies, the proposed scheme also improves the performance by up to 12%.

Two-Level Scratchpad Memory Architectures to Achieve Time Predictability and High Performance

In modern computer architectures, caches are widely used to shorten the gap between processor speed and memory access time. However, caches are time-unpredictable, and thus can significantly increase the complexity of worst-case execution time (WCET) analysis, which is crucial for real-time systems. This paper proposes a time-predictable twolevel scratchpad-based architecture and an ILP-based static memory objects assignment algorithm to support real-time computing. Moreover, to exploit the load/store latencies that are known statically in this architecture, we study a Scratchpad Sensitive Scheduling method to further improve the performance. Our experimental results indicate that the performance and energy consumption of the two-level scratchpad-based architecture are superior to the similar cache based architecture for most of the benchmarks we studied.

Architectural time-predictability factor (ATF)

Due to the prohibitive cost of worst-case timing analysis for modern processors, the design of time-predictable processors has become increasingly important for hard real-time and safety-critical systems. However, to the best of our knowledge currently there is no effective and widely accepted metric to quantitatively evaluate time predictability of processors, which greatly impedes the advancement of time-predictable processor design. This paper first introduces the concept of architectural time predictability (ATP), which separates timing uncertainty concerns caused by hardware from software. We then propose a metric called Architectural Time-predictability Factor (ATF) to measure architectural time predictability. Our evaluation on a Very Long Instruction Word (VLIW) processor indicates that ATF is an effective metric to quantitatively evaluate architectural time predictability of a whole processor as well as its architectural and microarchitectural components such as caches, branch prediction, speculative execution, parallel pipelines, and Scratch-Pad Memory (SPM). Thus ATF can be used to quantitatively guide architectural design for enhancing time predictability or making better trade-offs between performance and time predictability.

Design framework for FlexRay network parameter optimization

Because the FlexRay protocol has more than 70 configuration parameters and these parameters correlate with each other, designing a FlexRay network is a complex and difficult task. In this study, we propose a design framework that optimizes the two main FlexRay network parameters that are highly relevant to the application algorithm. The design process is composed of two steps for optimizing parameters. In the first step, the static slot length is optimized using a frame-packing algorithm. This algorithm binds network signals into static frames based on their periods and signal groups. In the second step, the communication cycle length is optimally designed with frame-scheduling algorithm and worst-case reponse time analysis. Based on the frame-scheduling algorithm, the response times are analyzed. The proposed design framework was applied to a unified chassis control system as a case study, and the analytical results were verified.