Worst-case Latency Research Articles

Decentralized deconfliction of aerial robots in high intensity traffic structures

AbstractProjections for future air mobility envisage intensely utilized airspace that does not simply scale up from existing systems with centralized air traffic control. This paper considers the implementation and test of a software and hardware framework for decentralized control of aerial vehicles within intensely used airspace. Up to 10 rotary wing vehicles of maximum all up mass of are flown in an outdoor volume with length scale of with GPS and WiFi connectivity. Flight control is implemented using a Pixhawk 4 flight controller running the PX4 firmware with guidance algorithms run on a separate onboard companion computer. Deconfliction is implemented using a simple elastic repulsion model with a guidance update rate of . Traffic structures are constructed from a path of directed waypoints and associated cross sectional geometry. Junctions are implemented when two paths converge into one or when one path diverges into two. Agents engage with structures through execution of flow, merge and swirl velocity rules. Calibration experiments showed that the worst case latency in agents sharing position information was of the order of made up from delays due to finite guidance update rate, WiFi processing and centralized message processing. A choice of vehicle cruise speed of and conflict radius of provided an acceptable compromise between experiment time efficiency (speed) and spatial efficiency (resolution) within the test volume. Results from recirculating junction experiments show that peak deconfliction activity occurs at the junction node, however biased distribution of agents within a corridor means the peak intensity is pushed ahead of the node. Use of meshed helical junction structures significantly reduces the intensity of conflict at the expense of reduced junction time efficiency.

A Worst-Case Latency and Age Analysis of Coded Distributed Computing With Unreliable Workers and Periodic Tasks

A Worst-Case Latency and Age Analysis of Coded Distributed Computing With Unreliable Workers and Periodic Tasks

Improving Worst-case TSN Communication Times of Large Sensor Data Samples by Exploiting Synchronization

Higher levels of automated driving also require a more sophisticated environmental perception. Therefore, an increasing number of sensors transmit their data samples as frame bursts to other applications for further processing. As a vehicle has to react to its environment in time, such data is subject to safety-critical latency constraints. To keep up with the resulting data rates, there is an ongoing transition to a Time-Sensitive Networking (TSN)-based communication backbone. However, the use of TSN-related industry standards does not match the automotive requirements of large timely sensor data transmission, nor it offers benefits on time-critical transmissions of single control data packets. By using the full data rate of prioritized IEEE 802.1Q Ethernet, giving time guarantees on large data samples is possible, but with strongly degraded results due to data collision. Resolving such collisions with time-aware shaping comes with significant overhead. Hence, rather than optimizing the parameters of the existing protocol, we propose a system design that synchronizes the transmission times of sensor data samples. This limits network protocol complexity and hardware requirements by avoiding tight time synchronization and time-aware shaping. We demonstrate that individual sensor data samples are transmitted without significant interference, exclusively at full Ethernet data rate. We provide a synchronous event model together with a straightforward response time analysis for synchronous multi-frame sample transmissions. The results show that worst-case latencies of such sample communication, in contrast to non-synchronized approaches, are close to their theoretical minimum as well as to simulative results while keeping the overall network utilization high.

A Reconfigurable Architecture for Real-time Event-based Multi-Object Tracking

Although advances in event-based machine vision algorithms have demonstrated unparalleled capabilities in performing some of the most demanding tasks, their implementations under stringent real-time and power constraints in edge systems remain a major challenge. In this work, a reconfigurable hardware-software architecture called REMOT, which performs real-time event-based multi-object tracking on FPGAs, is presented. REMOT performs vision tasks by defining a set of actions over attention units (AUs). These actions allow AUs to track an object candidate autonomously by adjusting its region of attention and allow information gathered by each AU to be used for making algorithmic-level decisions. Taking advantage of this modular structure, algorithm-architecture codesign can be performed by implementing different parts of the algorithm in either hardware or software for different tradeoffs. Results show that REMOT can process 0.43–2.91 million events per second at 1.75–5.45 W. Compared with the software baseline, our implementation achieves up to 44 times higher throughput and 35.4 times higher power efficiency. Migrating the Merge operation to hardware further reduces the worst-case latency to be 95 times shorter than the software baseline. By varying the AU configuration and operation, a reduction of 0.59–0.77 mW per AU on the programmable logic has also been demonstrated.

Euclidean-Division-Based Low-Complexity Precise Analytical Approach of BLE-Like Neighbor Discovery Latency

Neighbor discovery is the procedure to establish a first contact between two wireless devices. For duty-cycled low-power devices, energy consumption is closely related to neighbor discovery latency. Actually, in recent protocols, such as Bluetooth low energy (BLE) or ANT+, neighbor discovery latency is determined by the parameters used by the devices, such as advertising interval, scan window, scan interval, and so on. A fundamental problem of the BLE-like protocol is that the exact relation between parameters and discovery latency has not been fully analyzed. In this article, we propose a Euclidean-division-based low-complexity precise analytical approach that can derive the mathematical expressions of both worst-case latency and average latency for any parameter groups. It is confirmed by simulation results that our solution can make highly accurate predictions about the value of latencies. Simulation results also show that the proposed solution has an extremely low complexity. Moreover, we derive the lower bound of latency for given duty cycles, which provides useful guidelines for the choice of energy-efficient parameter groups for BLE.

Hardware Architecture for Reducing Worst-Case Latency in Fast SCF Polar Decoders

Hardware Architecture for Reducing Worst-Case Latency in Fast SCF Polar Decoders

HopliteML: Evolving Application Customized FPGA NoCs with Adaptable Routers and Regulators

We can overcome the pessimism in worst-case routing latency analysis of timing-predictable Network-on-Chip (NoC) workloads by single-digit factors through the use of a hybrid field-programmable gate array (FPGA)–optimized NoC and workload-adapted regulation. Timing-predictable FPGA-optimized NoCs such as HopliteBuf integrate stall-free FIFOs that are sized using offline static analysis of a user-supplied flow pattern and rates. For certain bursty traffic and flow configurations, static analysis delivers very large, sometimes infeasible, FIFO size bounds and large worst-case latency bounds. Alternatively, backpressure-based NoCs such as HopliteBP can operate with lower latencies for certain bursty flows. However, they suffer from severe pessimism in the analysis due to the effect of pipelining of packets and interleaving of flows at switch ports. As we show in this article, a hybrid FPGA NoC that seamlessly composes both design styles on a per-switch basis delivers the best of both worlds, with improved feasibility (bounded operation) and tighter latency bounds. We select the NoC switch configuration through a novel evolutionary algorithm based on Maximum Likelihood Estimation (MLE). For synthetic ( RANDOM , LOCAL ) and real-world ( SpMV , Graph ) workloads, we demonstrate ≈2–3× improvements in feasibility and ≈1–6.8× in worst-case latency while requiring an LUT cost only ≈1–1.5× larger than the cheapest HopliteBuf solution. We also deploy and verify our NoC (PL) and MLE framework (PS) on a Pynq-Z1 to adapt and reconfigure NoC switches dynamically. We can further improve a workload’s routability by learning to surgically tune regulation rates for each traffic trace to maximize available routing bandwidth. We capture critical dependency between traces by modelling the regulation space as a multivariate Gaussian distribution and learn the distribution’s parameters using Covariance Matrix Adaptation Evolution Strategy (CMA-ES). We also propose nested learning, which learns switch configurations and regulation rates in tandem. Compared with stand-alone switch learning, this symbiotic nested learning helps achieve ≈ 1.5× lower cost constrained latency, ≈ 3.1× faster individual rates, and ≈ 1.4× faster mean rates. We also evaluate improvements to vanilla NoCs’ routing using only stand-alone rate learning (no switch learning), with ≈ 1.6× lower latency across synthetic and real-world benchmarks.

A Low-Latency Streaming On-Device Automatic Speech Recognition System Using a CNN Acoustic Model on FPGA and a Language Model on Smartphone

This paper presents a low-latency streaming on-device automatic speech recognition system for inference. It consists of a hardware acoustic model implemented in a field-programmable gate array, coupled with a software language model running on a smartphone. The smartphone works as the master of the automatic speech recognition system and runs a three-gram language model on the acoustic model output to increase accuracy. The smartphone calculates and sends the Mel-spectrogram of an audio stream with 80 ms unit input from the built-in microphone of the smartphone to the field-programmable gate array every 80 ms. After ~35 ms, the field-programmable gate array sends the calculated word-piece probability to the smartphone, which runs the language model and generates the text output on the smartphone display. The worst-case latency from the audio-stream start time to the text output time was measured as 125.5 ms. The real-time factor is 0.57. The hardware acoustic model is derived from a time-depth-separable convolutional neural network model by reducing the number of weights from 115 M to 9.3 M to decrease the number of multiply-and-accumulate operations by two orders of magnitude. Additionally, the unit input length is reduced from 1000 ms to 80 ms, and to minimize the latency, no future data are used. The hardware acoustic model uses an instruction-based architecture that supports any sequence of convolutional neural network, residual network, layer normalization, and rectified linear unit operations. For the LibriSpeech test-clean dataset, the word error rate of the hardware acoustic model was 13.2% and for the language model, it was 9.1%. These numbers were degraded by 3.4% and 3.2% from the original convolutional neural network software model due to the reduced number of weights and the lowering of the floating-point precision from 32 to 16 bit. The automatic speech recognition system has been demonstrated successfully in real application scenarios.

Overview and Performance Evaluation of Wi-Fi 7

The arrival of Wi-Fi 6 in late 2019, which is based on IEEE 802.11 ax, marked a giant leap forward in improving the capacity, efficiency, and coverage in most WLAN environments. While Wi-Fi 6 introduced various features to enhance the network performance and user experience such as in high-dense deployment scenarios, emerging applications like 4K/8K video, augmented reality, virtual reality, industrial Internet of Things, and real-time collaborations demand more deterministic connectivity. Meeting the most stringent requirements in throughput and latency in a deterministic fashion is beyond the capabilities of Wi-Fi 6 and therefore motivates the development of a new Wi-Fi 7 generation. As a result, the IEEE 802.11 Task Group be has been formed to define extreme high throughput (EHT) PHY and MAC layers capable of supporting a maximum throughput of at least 30 Gb/s, as well as reducing worst case latency and jitter to improve support for latency-sensitive applications. In this article, our primary goal is to identify and describe the main PHY and MAC elements that will shape Wi-Fi 7, which will operate in the 2.4 GHz, 5 GHz, and 6 GHz bands. For each of the main features, including key PHY enhancements, multi-link operation, and enhanced quality of service management, we discuss how Wi-Fi 7 is designing the corresponding enabling mechanism and present performance results as appropriate.

Optimizing BLE-Like Neighbor Discovery

Neighbor discovery (ND) protocols are used for establishing a first contact between multiple wireless devices. The energy consumption and discovery latency of this procedure are determined by the parametrization of the protocol. In most existing protocols, reception and transmission are temporally coupled. Such schemes are referred to as <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">slotted</i> , for which the problem of finding optimized parametrizations has been studied thoroughly in the literature. However, slotted approaches are not efficient in applications in which new devices join the network gradually and only the joining devices and a master node need to run the ND protocol simultaneously. For example, this is typically the case in IoT scenarios or bluetooth low energy (BLE) piconets. Here, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">slotless</i> protocols that decouple reception and transmission can achieve significantly lower worst-case latencies than slotted ones. In this paper, we study slotless, BLE-like protocols, which schedule receptions and transmissions independently using periodic intervals (PI). For this class of protocols, optimal parameter values remain unknown. To address this, we propose an optimization framework for PI-based protocols, which translates any specified duty-cycle (and therefore energy budget) into a set of optimized parameter values. We show that the parametrizations resulting from one variant of our proposed scheme are optimal when one receiver discovers one transmitter, and no other parametrization or ND protocol – neither slotted nor slotless – can guarantee lower discovery latencies for a given duty-cycle in this scenario. Since the resulting protocol utilizes the channel more aggressively than other ND protocols, beacons will collide more frequently. Hence, due to collisions, the rate of successful discoveries gracefully decreases for larger numbers of devices discovering each other simultaneously. We also propose a scheme for configuring the BLE protocol (and not just BLE- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">like</i> protocols). Though it is not clear whether the resulting parametrizations minimize the latencies of BLE, reasonably low worst-case latencies can be guaranteed.

Multi-Objective Controller Failure Aware Capacitated Controller Placement in Software-Defined Networks

Software-Defined Networking disassociates the control plane from data plane. The problem of deciding upon the number and locations of controllers and assigning switches to them has attracted the attention of researchers. Foreseeing the possibility of failure of a controller, a backup controller has to be maintained for each switch so that the switches assigned to the failed controller can immediately be connected to their backup controllers. Hence, the switches cannot experience disconnections in case of failure of their controller. In this paper, two mathematical models are proposed. The first model focuses on minimizing the average of latencies from all switches to their backup controllers while considering the failure of the controllers. The second model aims at minimizing both the average and worst-case of latencies from all switches to the corresponding backup controllers. Both of our models are evaluated on three networks and are compared (in terms of two metrics, viz., average and worst-case latencies) with an existing model that focuses on minimizing only worst-case latency. The first model gives better average latency compared to the reference model. The second model also gives better average latency and almost equal worst-case latency compared to the reference model.

Extending MQTT with Real-Time Communication Services Based on SDN.

MQTT is one of the most popular application-layer protocols used in the scope of the Internet-of-Things (IoT) and Industrial-Internet-of-Things (IIoT), given its suitability for resource-constrained embedded systems. However, MQTT Quality-of-Service policies do not support timeliness requirements, which is common in IIoT. The literature reports several research works that address this limitation, but they are limited in scope (e.g., improvements in the broker’s internal operation, control of the publisher’s data rate, and path optimizations). Conversely, this paper presents a comprehensive architectural approach, proposing a set of extensions to the MQTT protocol that allow applications to explicitly specify real-time requirements and instantiate corresponding network reservations to enforce the desired temporal behavior. Such reservations are enforced via Software Defined Networking, specifically the OpenFlow protocol, but other protocols that allow bandwidth reservations, e.g., TSN, can also be used. This paper presents the proposed system architecture together with extensive emulation and implementation results that validate the feasibility of the approach, showing that time-sensitive MQTT traffic can be effectively segregated and prioritized to meet application-defined real-time requirements. Using several combinations of network topologies and load levels and comparing to the absence of the proposed real-time mechanisms, both average and worst-case latencies of the time-sensitive traffic decreased to approximately half, while for the normal traffic, they increased by approximately 10%.

Worst-Case Latency Analysis for AVB Traffic Under Overlapping-Based Time-Triggered Windows in Time-Sensitive Networks

Deterministic and low end-to-end latency communication is an urgent demand for many safety-critical applications such as autonomous vehicles and automated industries. The time-sensitive network (TSN) is introduced as Ethernet-based amendments in IEEE 802.1 TSN standards to support time-triggered (TT) traffic in these applications. In the presence of TT flows, TSN is designed to integrate Audio/Video Bridging (AVB) and Best Effort (BE) traffic types. Although AVB traffic has a lower priority than TT, it still requires low and deterministic latency performance, which may not be guaranteed under strict predefined TT scheduling constraints. For this reason, a window-overlapping scheduling algorithm is recently proposed in different works as analytical forms for TT latency under overlapping-windows based. But worst-case AVB latency evaluation under overlapped TT windows is also essential for critical optimizations and tradeoffs. In this paper, a worst-case end-to-end delay ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">WCD</i> ) for AVB traffic under overlapping-based TT windows (AVB-OBTTW) algorithm is proposed. Separate analytical models are derived using the network calculus (NC) approach for AVB-OBTTW with both non-preemption and preemption mechanisms. Using an actual vehicular use case, the proposed models are evaluated with back-to-back and porosity configurations under light and heavy loading scenarios. For specific AVB credit bounds, a clear <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">WCD</i> reduction has been achieved by increasing the overlapping ratio ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OR</i> ), especially under back-to-back configuration. Preemption and non-preemption modes are compared under different loading conditions, resulting in lower <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">WCD</i> s using preemption mode than non-preemption, especially with porosity style. Compared to the latest related works, AVB-OBTTW reduces <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">WCD</i> bounds and increases unscheduled bandwidth, leading to the highest enhancements with the maximum allowable <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OR</i> .

On Sequential Decoding Metric Function of Polarization-Adjusted Convolutional (PAC) Codes

In this paper, we present a sequential decoding metric function, which leads to significantly improved computational complexity while maintaining the superiority of polarization-adjusted convolutional (PAC) codes’ error-correction performance. With the proposed metric function, the PAC codes’ decoding computational complexity is comparable to the computational complexity of sequential decoding of conventional convolutional codes (CCs). Moreover, simulation results show an improvement in the error-correction performance of low rate PAC codes when using the proposed metric function. Simulation results also show that using the proposed metric, the upper bound on the PAC codes’ computational complexity has a Pareto distribution. To reduce the worst-case latency of PAC sequential decoder, we limit the number of searches performed by sequential decoder. The results show that for PAC codes of length 128, search-limited sequential decoding can achieve an error-correction performance close to the error-correction performance of polar codes with successive cancellation list decoding with list size 64 and CRC length 11 with considerably less computational complexity.

Protection switching schemes and mapping strategies for fail-operational hard real-time NoCs

Communication infrastructures designed for mixed-critical MPSoCs must provide isolation of traffic, hard real-time guarantees, and fault-tolerance. In previous work, we proposed the combination of protection-switching with a hybrid Time-Division-Multiplexed (TDM) and packet-switched Network-on-Chip (NoC) to achieve all three goals. In this paper, we present an FPGA implementation of such a NoC with all its features. We give synthesis results for the hybrid NoC, including the network interface, and show that our router uses over 32% fewer LUTs and registers than a competitive state-of-the-art router for mixed-critical MPSoC. We then explore different channel and task mapping strategies for critical applications which use protection switching and evaluate the effect these mappings have on the best-effort (BE) traffic in the system. Results show, that spreading out the critical traffic rather than naively dividing the system in critical and non-critical application domains is advantageous or even necessary in many cases and can allow for up to 13% more BE traffic. We give a comprehensive trade-off analysis of three protection switching schemes—1:n, 1:1, and 1+1—and show that 1+1 protection has less than half the worst case latency for critical traffic that 1:n and 1:1 protection have. At the same time, 1+1 protection, on average, only causes a 1.18% earlier saturation rate for BE traffic, which we consider to be affordable. We conclude that 1+1 protection is ideally suited for use in mixed-critical systems with high safety requirements.

Dynamic Priority-Based Computation Scheduling and Offloading for Interdependent Tasks: Leveraging Parallel Transmission and Execution

Mobile edge computing (MEC) has recently emerged as an effective paradigm to enhance the computing capability of capability-limited mobile devices (MDs). In this article, we consider an MEC system consisting of a number of MEC servers and one MD which generates a series of tasks characterized by their dependency relationships. We study computation scheduling and offloading problem of the tasks. To improve the task processing performance, we first propose a parallel transmission and execution (PTE) scheme, based on which we design a computation scheduling and offloading algorithm. Considering the fairness among tasks in terms of task transmission and execution time, we formulate the computation scheduling and offloading problem as a constrained worst-case latency optimization problem which minimizes the maximum completion time of all the tasks. As the original optimization problem cannot be solved conveniently, we first categorize the tasks into high priority tasks (HPTs), medium priority tasks (MPTs) and low priority tasks (LPTs) based on their task execution status and causal relationship. Then, a dynamic priority-based computation scheduling and offloading algorithm is proposed, which designs computation scheduling and offloading strategy for dynamically-changed HPTs and MPTs, respectively. In particular, for HPTs, a multiple knapsack-based heuristic algorithm is proposed, and a task weight and data size-based computation scheduling and offloading algorithm is further proposed for MPTs. Numerical results demonstrate the effectiveness of the proposed scheme.

Recorp: Receiver-oriented Policies for Industrial Wireless Networks

Future Industrial Internet-of-Things (IIoT) systems will require wireless solutions to connect sensors, actuators, and controllers as part of high data rate feedback-control loops over real-time flows. A key challenge in such networks is to provide predictable performance and adaptability in response to link quality variations. We address this challenge by developing RECeiver ORiented Policies (Recorp), which leverages the stability of IIoT workloads by combining offline policy synthesis and run-time adaptation. Compared to schedules that service a single flow in a slot, Recorp policies share slots among multiple flows by assigning a coordinator and a list of flows that may be serviced in the same slot. At run-time, the coordinator will execute one of the flows depending on which flows the coordinator has already received. A salient feature of Recorp is that it provides predictable performance: a policy meets the end-to-end reliability and deadline of flows when the link quality exceeds a user-specified threshold. Experiments show that across IIoT workloads, policies provided a median increase of 50% to 142% in real-time capacity and a median decrease of 27% to 70% in worst-case latency when schedules and policies are configured to meet an end-to-end reliability of 99%.

Deflection routing mechanism using BLESS and BBUS NoC

Buffer is a very crucial component in giving performance of an Network on Chip (NoC). In short buffers governs the performance of an NoC. But the major problem with Buffers is that they are power hungry. In these paper two types of deflection Routers have been discussed. One is BLESS (Buffer less Router) where total ordering sorting circuits is followed by a sequential port allocation while in second one total ordering is replaced with Golden Flit Concept. BLESS NoC includes hot potato routing including free live lock. As compared to normal VC Routers we are eliminating three stage sorting circuit. Rather than going for sequential port allocation we are going for parallel port allocation called as permutation deflection logic. Golden Flit concept together with permutation deflection logic is responsible for reduction of 29% of Routers Critical Path. Also clock based synchronization in CHIPPER based NoCs increases latency. To avoid this issue BBus NoC (Broadcast bus NoC) concept is discussed. The worst case latency is reduced by using Golden Flit concept.

Performance Assessment of Linux Kernels with PREEMPT_RT on ARM-Based Embedded Devices

This work investigates the real-time performance of Linux kernels and distributions with a PREEMPT_RT real-time patch on ARM-based embedded devices. Experimental measurements, which are mainly based on heuristic methods, provide novel insights into Linux real-time performance on ARM-based embedded devices (e.g., BeagleBoard and RaspberryPi). Evaluations of the Linux real-time performance are based on specific real-time software measurement modules, developed for this purpose, and the use of a standard benchmark tool, cyclictest. Software modules were designed upon the introduction of a new response task model, an innovative aspect of this work. Measurements include the latency of response tasks at user and kernel space, the response on the execution of periodic tasks, the maximum sustained frequency and general latency performance metrics. The results show that in such systems the PREEMPT_RT patch provides more improved real-time performance than the default Linux kernels. The latencies and particularly the worst-case latencies are reduced with real-time support, thus making such devices running Linux with PREEMPT_RT more appropriate for use in time-sensitive embedded control systems and applications. Furthermore, the proposed performance measurements approach and evaluation methodology could be applied and deployed on other Linux-based real-time platforms.

Real-Time Performance and Response Latency Measurements of Linux Kernels on Single-Board Computers

This research performs real-time measurements of Linux kernels with real-time support provided by the PREEMPT_RT patch on embedded development devices such as BeagleBoard and Raspberry Pi. The experimental measurements of the Linux real-time performance on these devices are based on real-time software modules developed specifically for the purposes of this research. Taking in consideration the constraints of the specific hardware platforms under investigation, new measurements software was developed. The measurement algorithms are designed upon response and periodic task models. Measurements investigate latencies of real-time applications at user and kernel space. An outcome of this research is that the proposed performance measurements approach and evaluation methodology could be applied and deployed on other Linux-based boards and platforms. Furthermore, the results demonstrate that the PREEMPT_RT patch overall improves the Linux kernel real-time performance compared to the standard one. The reduced worst-case latencies on such devices running Linux with real-time support could make them potentially more suitable for real-time applications as long as a latency value of about 160 μs, as an upper bound, is an acceptable safety margin.