Gate Work Function Research Articles

GeSn based heterojunction double-gate tripple metal layer vertical TFET with enhanced DC and Analog/RF performance

In this article, low-bandgap material GeSn and high bandgap Si material heterojunction (GeSn/Si) based double gate triple metal layer Vertical TFET is designed and analyzed by ATLAS Silvaco TCAD simulation tool. Higher ON-state current is obtained by this device owing to (i) the usage of novel low band-gap material i.e., GeSn and (ii) Vertical tunneling as the gate overlaps the source region. The incorporation of GeSn material not only enhances the ON-state current but also improves the SS, albeit trading off the OFF-state current and ambipolar current of the device. To control the ambipolar current and OFF-state current, variation in the gate to drain overlap and auxiliary gate metal work function has been done. The impact of the gate to drain overlap and auxiliary gate workfunction variation has been studied for various electrical parameters. Further through extensive simulation analysis, optimized dimensions have been obtained. An enormously high ION/IOFF ratio of the order of 1.6 × 1012, steepest point, and average subthreshold swing of 7.5 mV/dec and 12.3 mV/dec respectively has been achieved through this proposed device. In addition to this, comparison of the proposed device with other novel TFET devices reported in literature has been done. From the comparison, it has been concluded that better results are obtained by the proposed device in terms of ION, IAMB, ION/IOFF ratio, SSavg, and gm. Therefore, this novel proposed device can be used as a promising device for various small power applications. Further, this device not only provides improved DC and Analog/RF electrical parameters but also provides small footprint due to vertically aligned architecture.

Design and Performance Analysis of Partially Depleted and Fully Depleted Silicon on Insulator MOSFET

In this paper, Partially Depleted Silicon on Insulator (PDSOI) MOSFET and Fully Depleted Silicon on Insulator (FDSOI) MOSFET are designed, and the impact of n-type doping concentration, work function variation, gate oxide, and silicon layer thickness on the performance of the device is studied and analyzed. The floating body and associated kink effects present in a PDSOI device are also investigated in detail. In addition to this, comparisons are made between PDSOI and FDSOI MOSFET to analyze their performance for various device parameters. The threshold voltage rises with increasing Si surface thickness and source doping, according to the data found. The drain current increases as the N-type doping concentration develops in both PD and FDSOI MOSFETs, and conduction begins after a concentration of 3x1017 cm−3 for PD and 2x1017 cm−3 for FDSOI, before which conduction is not effective. For the same n-type doping concentration and gate work function, FDSOI has a higher drain current than PDSOI. FDSOI is better than PDSOI since it eliminates PDSOI’s defects and enhances its performance. The Silvaco Atlas-2D TCAD simulator is used to simulate the device using conventional architecture and models.

Research of Quantized Current Effect with Work Function Variation in Tunnel-field Effect Transistor

In this paper, an investigation has been performed to analyze the relation between on-current (ISUBon/SUB) and gate work function variation (WFV) in the tunnel field-effect transistor (TFET) with help of technology computer-aided design (TCAD) simulation. Comparing the ISUBon/SUB of metal-oxide-semiconductor field-effect transistor (MOSFET) and TFET, it is observed that the quantized current level of TFET is depending on channel bias conditions and width of channel. Therefore, we analyze this current quantization within three categorizations. Firstly, the ISUBon/SUB is quantized by applied level of high gate bias (VSUBGS/SUB). At high VSUBGS/SUB, the ISUBon /SUBis quantized well following gate WF value near the source-side because the tunnel barrier is made in the specific area by junction between gate and source. However, at low VSUBGS/SUB, a lot of current levels are confirmed because almost half of the channel is affected by WFV due to the large tunneling width. Secondly, the quantized ISUBon/SUB variation by WFV is also affected by level of VSUBDS/SUB. Because the influence of the channel potential is differed by induced electron density. Finally, the ISUBon/SUB is quantized by width of device. Because, considering metal grain size, the WF value near the source-side is determined only several levels. Then, related with the width, we quantitatively analyzed the quantization of ISUBon/SUB, and based on the probability of WFVs, it is confirmed that the phenomenon of current quantization in TFET is predictable.

Realization of Double‐Gate Junctionless Field Effect Transistor Depletion Region for 6 nm Regime with an Efficient Layer

Herein, the authors suggest a junctionless field effect transistor with an embedded p‐type layer (EPL‐JLT) near the drain channel side, employing calibrated structure simulations to obtain a complete depletion region in a 6 nm channel length. The incorporation of a p‐type layer improves leakage current (I OFF) and subthreshold swing (SS) for a 6 nm regime structure at 5.9 eV work function (WF) while the ON current (I ON) diminishes a little. This considerable achievement in the leakage current enables obtaining multiple threshold voltages (V TH) by adjusting the gate WF. The goal aids in creating optimized structures, which is impossible in silicon JLFETs (Si‐JLT) due to their requirement for large WFs to obtain a depletion region even at higher channel lengths. The proposed device has a leakage current of 1 nA μm−1 even at a 5.1 eV WF. The scaling of the EPL‐JLT for different channel lengths is investigated.

Field plated, gate work function engineered AlGaN channel HEMTs with improved DC, RF and power performance

This paper presents the study of the impact of gate work function engineering on the performance of AlGaN channel high electron mobility transistor. The proposed devices with dual material and triple material gate structures result in improved electrical characteristics. The devices exhibit a peak transconductance of 11.86 mS, 11.80 mS respectively for triple and dual material gate structures. A comparative analysis on the performance of the proposed device structures with that of a conventional AlGaN channel HEMT is presented. The devices are able to offer superior RF performance compared to the conventional device with fT values of 0.89 GHz, 0.889 GHz for triple material and dual material gate devices respectively. By incorporating gate field plates, field crowding at the gate edge can be reduced further. The field plated structure can cater to better high voltage operation with a slight penalty on the high frequency performance.

Performance Assessment and Optimization of Vertical Nanowire TFET for Biosensor Application

This paper reports the performance assessment of vertical silicon nanowire TFET (V-siNWTFET) design for biosensor applications using dielectric-modulation and gate underlap technique. The sensitivity of the V-siNWTFET is recognizing by immobilizing the different biological molecules such as lipids, biotin, uricase, protein, Gox, streptavidin, uriease, zein etc. in the cavity region which is created under the gate electrode and source oxide. The performance analysis is observed by varying the relative permittivity of the different biomolecules and analyzes the parametric variation both for neutral and charged biomolecules. The sensitivity of the biosensor has been detecting in the terms of drain current (ID), threshold voltage (VTH), subthreshold slope (SS), transconductance (gm), and ION/IOFF ratio. The proposed device structure has capable to reduce the leakage currents and high sensitivity biosensor design in the nanoscale regimes. The obtained best optimum parameters of the proposed devices are ION (1.37E−08 A/µm), IOFF (9.44E−19 A/µm), SS (29.97 mV/dec) and ION/IOFF (4.29E + 10) ratio with gate work-function (ϕgate = 4.8 eV) and uniformly doped (1 × 10–19 cm−3) silicon nanowire at drain to source voltage (VDS = 1.0 V). The higher sensitivity of the proposed V-siNWTFET for Biosensor is observed for Zein biomolecules (K = 5).

Design and investigation of dielectric modulated triple metal gate-oxide-stack Z-shaped gate horizontal pocket TFET device as a label-free biosensor

In this article, a dielectric modulated triple metal gate-oxide-stack Z-shaped gate horizontal source pocket tunnel field-effect transistor (DM-TMGOS-ZHP-TFET) structure has been investigated for the application of label free-biosensor. This work explores the advantage of gate work function engineering along with the gate-oxide-stack approach for the ZHP-TFET for the first time. An asymmetric nano-cavity is created adjacent to the source-channel junction to immobilize the target biomolecules conjugation to the proposed device. The sensitivity of the device is thoroughly investigated in terms of average subthreshold swing (SS), threshold voltage (V th) and the switching ratio (I on/I off) of the proposed device with the variation of the dielectric constant value inside the nano-gap under the gate electrode. The device characteristics are investigated with different combinations of metal work functions to match the desired feature and sensitivity of the device. In addition, the sensitivity analysis of the proposed device is analyzed in the presence of both positive and negative charged biomolecules in the cavity region to study the charge effect on label-free detection of the device. A comparative study is conducted between a single metal gate (SMG) ZHP-DM-TFET biosensor with the DM-TMGOS-ZHP-TFET biosensor explores the advantage of gate-work function engineering with a gate-oxide-stack approach. Interestingly the DM-TMGOS-ZHP-TFET biosensor shows superior results with a high current ratio sensitivity of 103 which is ten times more than the SMG-ZHP-DM-TFET biosensor and this device also exhibits low subthreshold characteristics.

A Ballistic Transport Nanodevice Based on Graphene Nanoribbon FET by Enhanced Productivity for Both Low-Voltage and Radio-Frequency Scopes

The top performance in both the low-voltage and radio frequency (RF) scopes has been nominated for an unique nanodevice made from a graphene nanoribbon with an extremely short gate length (7.5 nm) in this study. Two distinct material engineering options were used, yielding some interesting outcomes. Due to the use of an ultrascale GNRFET in this study, the band structure non-linearity in the Dirac point and the energy-position dependent effective mass model for dual material gate architectures were examined for the first time. The NEGF formalism is used to carry out both the low-voltage and RF research using a three-dimensional (3D) Poisson equation. Low-voltage high performance has been validated by monitoring the key parameters in the terms of on current (Ion), off current (Ioff), Ion to Ioff ratio, subthreshold swing, and drain induced barrier lowering (DIBL) for the proposed device as compared to other structures under the study. The RF performance is examined by evaluation of essential parameters in the cases of parasitic gate capacitance, intrinsic cut-off frequency, intrinsic delay time, and transconductance. Indeed, a device with a higher source side gate work function than it does on the drain side is proposed will shift the energy band from the device’s half to the drain electrode, altering carrier outflow. In addition, the performance of non-linearity and RF intermodulation distortion has been analyzed for all devices under investigation in order to attain the best attitude toward the suggested device in comparison to the other devices under investigation in this work.

A Computationally Efficient Model for FDSOI MOSFETs and Its Application for Delay Variability Analysis

This paper proposes a compact, physics-based current model for fully depleted silicon-on-insulator (FDSOI) MOSFETs and applies it to delay variability analysis. An analytical method is applied to avoid the numerical iterations required in the evaluation of surface potential, which directly improves the computational efficiency. The accuracy of the explicit surface potential approximation is 190.3 nV, which allows for fast convergence. Surface potential and current calculations achieve 1.8× and 1.4× acceleration compared with BSIM-IMG, respectively. To establish the relationship between delay and underlying process parameters, we introduce the effective current and propose a process variation-aware delay prediction model. Higher-order derivatives are calculated to compensate the nonlinearity of delay variations with respect to process parameters. Experiments show a significant improvement in the prediction accuracy with higher-order derivatives, which are proved to be able to handle nonlinearity under process variations. The front gate work function contributes the most to the nonlinearity of the delay variation and the accuracy of the third-order prediction is 4.07%. Under the variation in the channel length and width, front and back gate oxide thickness and body thickness, delay variations have similar characteristics and the second-order prediction is found to be sufficient to model the nonlinearity with a maximum relative error of 1.22%. The delay prediction model only requires a single-point HSPICE DC or transient simulation and is universal for different voltages and different cells. Compared with the Monte Carlo (MC) simulation, the accuracy of the first-order prediction in the above-threshold region (0.8 V) is 0.94%. In the sub-threshold region (0.3 V), a prediction accuracy of 2.01% can be obtained while achieving a 21× reduction in computational time.

Analysis of total ionizing dose response of optimized fin geometry workfunction modulated SOI-FinFET

The total ionizing dose (TID) response of SOI-FinFET with linear gate workfunction modulation is presented and evaluated. The gate metal workfunction is linearly modulated from source to drain to maintain the electrostatic integrity of the device. At the higher radiation dose (2000 krad), the proposed device has shown reduced Off-current by 2-decade leads to improvement in current switching ratio. Moreover, the proposed device offers 9% and 3% improvement in subthreshold swing before and after the radiation, respectively. During irradiation the trap charges are found in the BOX layer and SiO2/Si interface. These charges contributed towards shifting of threshold voltage (Vth). The linear workfunction modulation shows a 73% more Vth as compared to single workfunction FinFET for radiation of 2000 krad dose. As per simulation results, the proposed device is reliable and capable to sustain in the radiation environment.

Drain-Engineered Reconfigurable Transistor Exhibiting Complementary Operation

In this paper, we propose and simulate a multifunctional transistor that exhibits device reconfigurability and realizes both nFET and pFET electrical characteristics when adequately biased. The use of this device will significantly reduce the transistor count in realizing sequential and combinational circuits and will result in highly compact design. The device uses a dual fin structure having a single mid-gap workfunction gate (\(\sim \)4.65 eV) alongside dual metal (metal-silicide) drain regions. It employs n+/p+-i junctions at the source-channel interface along with the Schottky junctions at the channel-drain interface. In practice, metal-silicides such as erbium/ytterbium silicide (ErSix/YbSix) for the n-drain and platinum silicide (PtSi) for the p-drain can be used as they provide smallest electron and hole Schottky-barrier heights (SBHs). Simulations carried out using calibrated parameters show better drive current (≈ 10− 2 − 10− 3A/μ m) compared to the quantum tunneling current in simulated state-of-the-art multifunctional devices (≈ 10− 4 − 10− 5A/μ m). In addition, butterfly curves show symmetric high (NMH) and low (NML) noise margins of 0.43V and 0.29V for zero and finite SBHs, respectively. The switching characteristics is shown to have an overshoot of \(\sim \)0.15 V for realistic SBHs which is then eliminated for the case of zero SBHs. In the last section, it is also demonstrated that a simplified structure having single mid-gap workfunction (\(\sim \)4.65 eV) drain of Nickel silicide (NiSi) does not hamper the reconfigurability of the device.

Variability analysis of the epitaxial layer TFET due to gate work function variation, random dopant fluctuation, and oxide thickness fluctuation using the statistical impedance field method

In this paper, a comparative study on process variability considering work function variation (WFV), random dopant fluctuation (RDF), and oxide thickness fluctuation (OTF) in epitaxial layer tunnel field effect transistor (TFET) with SiGe source (SiGe-ETLTFET) is statistically analyzed using impedance field method (IFM) in Santaurus TCAD tool. Effect of different grain sizes of the gate metal and other device parameter scaling on the variability source are investigated by evaluating the standard deviation of threshold voltage (V th), on current (I ON), and off current (I OFF). At smaller AverageGrainSize, the dispersions in electrical parameters are close to normal, whereas for large AverageGrainSize dispersion increases and deviates from the normal distribution. Compared to RDF and WFV, OTF is not a significant cause of variability in SiGe-ETLTFET. It is found that RDF is the most sensitive variability source while device scaling is concerned. Moreover, L ov scaling causes the most acute fluctuation of electrical parameters for all considered variability sources. The slope of the Pelgrom plot, A VT, of SiGe-ETLTFET considering all variability sources, is smaller than the already reported values for the FinFET and MOSFET.

First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3-D Integration With Dual Work Function Gate for Ultralow-Power SRAM and RF Applications

In this article, heterogeneous complementary field-effect-transistor (CFET) constructed by vertically stacking amorphous indium gallium zinc oxide (a-IGZO) n-channel on poly-Si p-channel with their own dielectric layer and work function metal gate inverters were demonstrated. Meanwhile, high-frequency IGZO radio frequency (RF) devices with poly-Si as guard ring material simultaneously were fabricated in the same process. High <inline-formula> <tex-math notation="LaTeX">${f}_{\text {T}}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">${f}_{\text {max}}$ </tex-math></inline-formula> IGZO Radio Frequency Integrated Circuits (RFICs) with the excellent on&#x2013;off ratio need to be promoted by introducing fluorine-based gas. For the IGZO device in CFET, its threshold voltage can be tuned by the adjusted gate for ideal inverter operation at different supply voltage (<inline-formula> <tex-math notation="LaTeX">${V}_{\text {DD}}$ </tex-math></inline-formula>). Moreover, the swing of the IGZO transistor and the gain extracted from voltage transfer characteristic (VTC) curves can also be improved when the controlled gate and adjusted gate are connected as an input terminal, but the <inline-formula> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> tunability for the inverter is satisfied in the meantime. We also simulated 6T-SRAM circuit by SPICE model to further investigate the potential of an adjusted gate for optimizing the noise margin during SRAM operation.

Design and investigation of field plate-based vertical GAA – β-(AlGa)2O3/Ga2O3 high electron mobility transistor

In this work, a novel Gate-all-around β-(AlGa)2O3/Ga2O3 HEMT device with Al2O3 as a passivation layer using gate connected field plate technique has been proposed. Proposed device results in improved breakdown voltage and out power density. To investigate intensively, field plate length has been varied from 0.5 ​μm to 2.5 ​μm and effects of variation are analyzed on analog as well as linearity parameters. At 2.5 ​μm field plate length, considered device exhibited peak breakdown voltage and out power density of 915 ​V and 21.8 ​KW respectively. At proposed field plate length (=2.5 ​μm), effects of gate electrode are comprehensively investigated by varying gate length and work function. For analysis, gate length is varied from 0.5 ​μm to 1 ​μm and work function varied from 5.1eV to 6.0eV. In future, proposed device can be used in power switching applications such as telecommunication, factory automation and motor control.

Role of gate electrode in influencing interface trap sensitivity in SOI tunnel FETs

This article reports the response of a silicon-on-insulator tunnel field-effect transistor (TFET) to the presence of semiconductor/ gate dielectric interface traps. A systematic strategy is designed keeping in view different parameters which are related to the gate of the device. Acceptor-like traps, and donor-like traps with Gaussian distribution are considered at the said interface for the entire analysis. Sensitivity % is taken as a figure of merit which measures the deviation of the drain current in presence of traps from the cases with no traps. The effect of temperature on interface traps, and the effect of interface traps on gate leakage current are analyzed. The acceptor-like traps are found to affect the on-state regime, and the donor-like traps are found to affect the ambipolar regime. Analyses on gate–drain underlap, gate–source overlap, shift of entire gate over the device, and gate work-function suggest that the gate electrode plays an important role in determining the sensitivity of the TFETs. Furthermore, noise spectral densities in presence of flicker, diffusion, and monopolar generation-recombination noise sources, and interface traps are reported.

Undoped Drain Graded Doping (UDGD) based TFET design: An innovative concept

The work deals with the implementation of charge plasma concept towards the formation of graded doping profile in the Drain region of Tunnel FET (TFET) device architecture. This new and innovative concept of graded doping profile in the lateral direction holds its merit towards stopping the ambipolar conduction in TFETs without affecting its off and the on state performance. The proposed device i.e. Undoped Drain Graded Doping based TFET (UDGD TFET) architecture is highly effective in suppressing the gate to drain and therefore the total gate capacitance values and thus also seems promising towards reduction in the dynamic power dissipation in TFETs. The architecture has also shown significant improvements for RF application in terms of cut-off frequency, Gain Bandwidth and Transit Time with optimized parameters such as gate work function, drain workfunction, channel length and drain region length when compared to conventional Tunnel FETs.

Wrapped Channel FET (WCFET)

In this article, we examined the electrical characteristic of proposed new device structure, Wrapped Channel Field Effect Transistor (WCFET). Results of WCFET have been analyzed using Atlas 3-D simulator. WCFET shows better transfer characteristics with ON-current ION of ~10-6A and leakage current IOFF of ~10-16 A. Optimization of device characteristics has done with doping concentration (ND), gate work function (ΦG) and spacer dielectric. Impact of gate length and semiconductor film thickness variation on drain current, subthreshold slope (SS) and DIBL are also investigated. Further, effects of various gate dielectric materials such as SiO2, Si3N3, HfO2 and TiO2 are examined w.r.t. switching characteristics of WCFET. To validate of device compatibility with power supply scaling, we inspected full range variation of VDS ≈ (0.05V-to-0.7V) on transfer characteristics.

The Effect of Gate Work Function and Electrode Gap on Wide Band-Gap Sn-Doped α-Ga2O3 Metal-Semiconductor Field-Effect Transistors.

We present technology computer aided design (TCAD) results for wide band-gap Sn-doped α-Ga2O3 metal–semiconductor field-effect transistors (MESFETs). In particular, the effect of gate work function and electrode gap length on the electrical characteristics is demonstrated for a thorough understanding of the behavior of such devices. The gate work function significantly affects the reverse bias drain current under the gate-current dominant regime, whereas a gate-source/drain gap larger than 0.1 µm has a negligible effect on the drain current.

Modeling of 7 Nano Meter Fin Field Effect Transistor for Evaluation of Fringe &amp; Oxide Capacitance

Fin-FET are insusceptible to short channel effects punch through, threshold voltage, leakage current but their concerts at high frequencies are conceded due to durable fringing field between gate and source with drain area. Because of high-technology progression, the gate construction of MOSFET has been upgraded from planar to nonplanar with an enrichment in the number of monitoring gates multiple gates on 3 sides. In this paper we mention Fin-FET assembly for high frequency applications.&#x0D; MOS-FET plays very energetic role but scaling of device affected on performance parameters like speed and power. Fin-FET is non planar novel device to solve the short channel effects which occurs due to scaling. Non-planar structure of Fin-FET parasitic capacitances like gate oxide overlap and fringe capacitance makes adverse effect like lower switching speed of device, making result on delay ion and ioff of device. In this paper we planned Fin-FET design procedure to measure oxide and fringe capacitance with low k dielectric spacer thickness and increase ion to recover device driving ability. Effect on threshold voltage having observed with low k spacer at least count of 0.051 V. By using 4.65 eV metal gate work function with front, top and back gate we control leakage current and threshold voltage. Seven nano meter gate length Fin-FET is design We measured oxide capacitance of 0.464 F for 19.28 GHz and fringe capacitance (69.66 nf) for 4.88 GHz frequency by designing the Fin-FET with high-K SOI MOSFETs which support 11.4 nA leakage current to improve the speed of the processor.&#x0D; In this research work, design topologies of Single Finger Fin Filed Effect Transistors are discussed and evaluate the probable result of fringe and parasitic capacitance from fringing area on the device. By using geometry of device like fin width, height, thickness and multiple fingers we measure the fringe capacitance and oxide capacitance of designed Fin-FET.&#x0D; HIGHLIGHTS&#x0D; &#x0D; In this Paper, we focus on fundamentals of novel device Fin-FET its working construction &amp; design based on geometry parameter &amp; capacitance measurement by designing model of 7 nm gate length&#x0D; In this work, we focus on how Fin-FET helps to reduce short channel effect by possessions of geometry parameters like gate length and Fin thickness &amp; progress the performance of the nanoscale device&#x0D; From the simulation results we observe lowering of drain induced barrier lowering, subthreshold slope and leakage current, whereas threshold voltages rise&#x0D; From the observation, SCE has been attributed to the distribution of the junction electric fields into the channel region, producing lower DIBL which decreases VTH&#x0D; &#x0D; GRAPHICAL ABSTRACT

Implementation of a Linearly Graded Binary Metal Gate Work Function VTFET with Air Pocket

Implementation of a Linearly Graded Binary Metal Gate Work Function VTFET with Air Pocket