Metal Gate Work Function Research Articles

Novel Modeling Approach to Analyze Threshold Voltage Variability in Short Gate-Length (15-22 nm) Nanowire FETs with Various Channel Diameters.

In this study, threshold voltage (Vth) variability was investigated in silicon nanowire field-effect transistors (SNWFETs) with short gate-lengths of 15–22 nm and various channel diameters (DNW) of 7, 9, and 12 nm. Linear slope and nonzero y-intercept were observed in a Pelgrom plot of the standard deviation of Vth (σVth), which originated from random and process variations. Interestingly, the slope and y-intercept differed for each DNW, and σVth was the smallest at a median DNW of 9 nm. To analyze the observed DNW tendency of σVth, a novel modeling approach based on the error propagation law was proposed. The contribution of gate-metal work function, channel dopant concentration (Nch), and DNW variations (WFV, ∆Nch, and ∆DNW) to σVth were evaluated by directly fitting the developed model to measured σVth. As a result, WFV induced by metal gate granularity increased as channel area increases, and the slope of WFV in Pelgrom plot is similar to that of σVth. As DNW decreased, SNWFETs became robust to ∆Nch but vulnerable to ∆DNW. Consequently, the contribution of ∆DNW, WFV, and ∆Nch is dominant at DNW of 7 nm, 9 nm, and 12, respectively. The proposed model enables the quantifying of the contribution of various variation sources of Vth variation, and it is applicable to all SNWFETs with various LG and DNW.

Analysis of total ionizing dose response of optimized fin geometry workfunction modulated SOI-FinFET

The total ionizing dose (TID) response of SOI-FinFET with linear gate workfunction modulation is presented and evaluated. The gate metal workfunction is linearly modulated from source to drain to maintain the electrostatic integrity of the device. At the higher radiation dose (2000 krad), the proposed device has shown reduced Off-current by 2-decade leads to improvement in current switching ratio. Moreover, the proposed device offers 9% and 3% improvement in subthreshold swing before and after the radiation, respectively. During irradiation the trap charges are found in the BOX layer and SiO2/Si interface. These charges contributed towards shifting of threshold voltage (Vth). The linear workfunction modulation shows a 73% more Vth as compared to single workfunction FinFET for radiation of 2000 krad dose. As per simulation results, the proposed device is reliable and capable to sustain in the radiation environment.

Design and analysis of dopingless 1T DRAM using work function engineered tunnel field effect transistors

In this paper, a dopingless DRAM based on work function engineered Tunnel field effect transistor is proposed. Gate metal workfunction engineering is done to enhance ON/OFF current ratio of drain current, thereby improving the sense margin and retention time. Drain electrode is made up of dual metal, so as to suppress ambipolar current. The analysis of dual material gate dual drain electrode DRAM (DMG DDE DRAM) and triple material gate dual drain electrode DRAM (TMG DDE DRAM) is done in terms of retention time and sense margin. The performance parameters with different device dimensions and bias conditions are analyzed. It is observed that the proposed DRAMs work well even when the dimensions are scaled down. In addition, the proposed DRAMs have comparable performance with the conventional DRAMs and provide better performance when compared with other dopingless DRAM. Retention times of 430 ms and 370 ms, sense margins of 130 nA and 101 nA are achieved with TMG DDE DRAM and DMG DDE DRAM respectively.

Top gate engineering of field-effect transistors based on wafer-scale two-dimensional semiconductors

l The threshold voltage of the MoS 2 field-effect transistor was controlled by the work function of top gate metal (Au, Cu, Ag, and Al). l The oxidation of the Al gate produced surplus oxygen vacancy (positive charge) and the dipole effect in the HfO 2 dielectric layer. l Transmission electron microscope was employed to explore the thin Al 2 O 3 interlayer in the Al/HfO 2 interface. l The proposed MoS 2 inverter has an optimized inverter switching threshold voltage and DC voltage gain, which possesses significant potential for integrated multistage logic circuits. The investigation of two-dimensional (2D) materials has advanced into practical device applications, such as cascaded logic stages. However, incompatible electrical properties and inappropriate logic levels remain enormous challenges. In this work, a doping-free strategy is investigated by top gated (TG) MoS 2 field-effect transistors (FETs) using various metal gates (Au, Cu, Ag, and Al). These metals with different work functions provide a convenient tuning knob for controlling threshold voltage ( V th ) for MoS 2 FETs. For instance, the Al electrode can create an extra electron doping (n-doping) behavior in the MoS 2 TG-FETs due to a dipole effect at the gate-dielectric interface. In this work, by achieving matched electrical properties for the load transistor and the driver transistor in an inverter circuit, we successfully demonstrate wafer-scale MoS 2 inverter arrays with an optimized inverter switching threshold voltage ( V M ) of 1.5 V and a DC voltage gain of 27 at a supply voltage ( V DD ) of 3 V. This work offers a novel scheme for the fabrication of fully integrated multistage logic circuits based on wafer-scale MoS 2 film.

First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3-D Integration With Dual Work Function Gate for Ultralow-Power SRAM and RF Applications

In this article, heterogeneous complementary field-effect-transistor (CFET) constructed by vertically stacking amorphous indium gallium zinc oxide (a-IGZO) n-channel on poly-Si p-channel with their own dielectric layer and work function metal gate inverters were demonstrated. Meanwhile, high-frequency IGZO radio frequency (RF) devices with poly-Si as guard ring material simultaneously were fabricated in the same process. High <inline-formula> <tex-math notation="LaTeX">${f}_{\text {T}}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">${f}_{\text {max}}$ </tex-math></inline-formula> IGZO Radio Frequency Integrated Circuits (RFICs) with the excellent on&#x2013;off ratio need to be promoted by introducing fluorine-based gas. For the IGZO device in CFET, its threshold voltage can be tuned by the adjusted gate for ideal inverter operation at different supply voltage (<inline-formula> <tex-math notation="LaTeX">${V}_{\text {DD}}$ </tex-math></inline-formula>). Moreover, the swing of the IGZO transistor and the gain extracted from voltage transfer characteristic (VTC) curves can also be improved when the controlled gate and adjusted gate are connected as an input terminal, but the <inline-formula> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> tunability for the inverter is satisfied in the meantime. We also simulated 6T-SRAM circuit by SPICE model to further investigate the potential of an adjusted gate for optimizing the noise margin during SRAM operation.

Importance of Charge Trapping/Detrapping Involving the Gate Electrode on the Noise Currents of Scaled MOSFETs

Carrier trapping/detrapping from/to the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gate</i> into dielectric traps is often neglected when modeling noise in MOSFETs and, to the best of our knowledge, no systematic study of its impacts on scaled devices is available. In this article, we show that this trapping mechanism cannot be neglected in nowadays aggressively scaled gate dielectric thicknesses without causing errors up to several orders of magnitude in the estimation of the drain current noise. The noise generation mechanism is modeled analytically and then analyzed through the use of 2-D and 3-D TCAD simulations of scaled MOSFETs with different architectures and channel/gate-stack materials. The results provide new insights for technology and device designers, highlight the relevance of the choice of the gate metal work function (WF) and the role of valence band electron trapping at high gate voltages.

Design of JL-CFET (junctionless complementary field effect transistor)-based inverter for low power applications

Junctionless complementary field effect transistor (JL-CFET) is an emerging device that needs a small layout area and low fabrication cost. However, in order for the JL-CFET to be adopted for low power applications, two main constraints need to be overcome: (a) a high work function of metal gate and (b) a low drain current. In this work, an optimal device design is proposed to overcome those problems, by analyzing various performance metrics, such as on-state drive current, subthreshold swing, drain induced barrier lowering, propagation delay time, and ring oscillator’s oscillation frequency, which are extracted from various structures of JL-CFET. In addition, the negative capacitance effect in JL-CFET is examined to address the limit from device structures.

Development of an analytical model of work function modulated GAA MOSFET for electrostatic performance analysis

This paper describes a continuous and almost linearly modulated work-function adjustment between 4.8–4.2eV using Hf-Mo binary alloy. The work-function modulated (WM) metal gate is applied to a gate all around MOSFET (GAA) for better electrostatic control. The threshold voltage is tuned by linearly modulating the gate metal work function. The threshold voltage extracted for dual-GAA MOSFET is initially 0.705 V. However, introducing work-function modulation, the threshold voltage is shifted to 0.620 V for WMGAA and 0.632 V for dual-WMGAA MOSFET. The simulation results validate the benefits of using work-function modulated metal gate in place of normal metal gate in terms of electron mobility, threshold voltage (Vth), and drain current (Id). An improved device performance with reduced short channel effect shows the capability of this device for various circuit applications.

Modeling of 7 Nano Meter Fin Field Effect Transistor for Evaluation of Fringe &amp; Oxide Capacitance

Fin-FET are insusceptible to short channel effects punch through, threshold voltage, leakage current but their concerts at high frequencies are conceded due to durable fringing field between gate and source with drain area. Because of high-technology progression, the gate construction of MOSFET has been upgraded from planar to nonplanar with an enrichment in the number of monitoring gates multiple gates on 3 sides. In this paper we mention Fin-FET assembly for high frequency applications.&#x0D; MOS-FET plays very energetic role but scaling of device affected on performance parameters like speed and power. Fin-FET is non planar novel device to solve the short channel effects which occurs due to scaling. Non-planar structure of Fin-FET parasitic capacitances like gate oxide overlap and fringe capacitance makes adverse effect like lower switching speed of device, making result on delay ion and ioff of device. In this paper we planned Fin-FET design procedure to measure oxide and fringe capacitance with low k dielectric spacer thickness and increase ion to recover device driving ability. Effect on threshold voltage having observed with low k spacer at least count of 0.051 V. By using 4.65 eV metal gate work function with front, top and back gate we control leakage current and threshold voltage. Seven nano meter gate length Fin-FET is design We measured oxide capacitance of 0.464 F for 19.28 GHz and fringe capacitance (69.66 nf) for 4.88 GHz frequency by designing the Fin-FET with high-K SOI MOSFETs which support 11.4 nA leakage current to improve the speed of the processor.&#x0D; In this research work, design topologies of Single Finger Fin Filed Effect Transistors are discussed and evaluate the probable result of fringe and parasitic capacitance from fringing area on the device. By using geometry of device like fin width, height, thickness and multiple fingers we measure the fringe capacitance and oxide capacitance of designed Fin-FET.&#x0D; HIGHLIGHTS&#x0D; &#x0D; In this Paper, we focus on fundamentals of novel device Fin-FET its working construction &amp; design based on geometry parameter &amp; capacitance measurement by designing model of 7 nm gate length&#x0D; In this work, we focus on how Fin-FET helps to reduce short channel effect by possessions of geometry parameters like gate length and Fin thickness &amp; progress the performance of the nanoscale device&#x0D; From the simulation results we observe lowering of drain induced barrier lowering, subthreshold slope and leakage current, whereas threshold voltages rise&#x0D; From the observation, SCE has been attributed to the distribution of the junction electric fields into the channel region, producing lower DIBL which decreases VTH&#x0D; &#x0D; GRAPHICAL ABSTRACT

Implementation of a Linearly Graded Binary Metal Gate Work Function VTFET with Air Pocket

Implementation of a Linearly Graded Binary Metal Gate Work Function VTFET with Air Pocket

Feasibility Study of Tuning the Threshold Voltage of Nanoscale Fin-shaped Field Effect Transistor (FinFET) via Metal Gate Workfunction Engineering

Feasibility Study of Tuning the Threshold Voltage of Nanoscale Fin-shaped Field Effect Transistor (FinFET) via Metal Gate Workfunction Engineering

Gated silicon nanowire for thermo-electric power generation and temperature sensing

Gate-all-around Si FETs are predicted to be the future of integrated CMOS circuits (ICs). The reduction in size of the Si channel, surrounded by oxide and a gate causes increased self-heating effects due to a reduction in thermal conductivity of the Si channel. Although, this degrades performance, we demonstrate that this can be exploited for localized thermoelectric power generation and temperature sensing that help reduce energy waste and increase IC lifetime. We show, using Sentaurus TCAD simulations, that unbiased gated intrinsic Si nanowires (NWs) can generate 2.2 times higher output power than doped NWs by choosing the correct metal gate work function. In addition, the voltage on the gate of the NW can be used to sense the temperature at the hot-spot in gate-all-around ICs. Among the studied gated NWs, the double gated structure with 30 nm gate length shows higher sensitivity to the change of temperature.

Understanding the Origin of Metal Gate Work Function Shift and Its Impact on Erase Performance in 3D NAND Flash Memories.

We studied the metal gate work function of different metal electrode and high-k dielectric combinations by monitoring the flat band voltage shift with dielectric thicknesses using capacitance–voltage measurements. We investigated the impact of different thermal treatments on the work function and linked any shift in the work function, leading to an effective work function, to the dipole formation at the metal/high-k and/or high-k/SiO2 interface. We corroborated the findings with the erase performance of metal/high-k/ONO/Si (MHONOS) capacitors that are identical to the gate stack in three-dimensional (3D) NAND flash. We demonstrate that though the work function extraction is convoluted by the dipole formation, the erase performance is not significantly affected by it.

TCAD Based Investigation of Single Event Transient Effect in Double Channel AlGaN/GaN HEMT

In this paper, investigation of Double Channel (DC) AlGaN/GaN HEMT has been presented using extensive TCAD simulation under the influence of Single Event Transient (SET) effect. Various models used to emulate Single Channel (SC) and DC HEMT in the TCAD are calibrated with the help of previously reported work. In order to present clear insight into the device behaviour, thermal model has also been included during device simulation. Presented results show that the generation of electron-hole pair due to heavy ion beam is significantly higher in DC HEMT during both OFF and ON state conditions. Ion beam having different Linear Energy Transfer (LET) and different position of Ion strike along with penetration depth has been used for investigating the SET effect on DC and SC AlGaN/GaN HEMT. The suitability of different metal gate work-function for heavy Ion detection has also been performed using both devices and DC HEMT (0.115 A/mm) demonstrated superior \bigtriangleup I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> DMAX</sub> as compared to SC HEMT (0.049 A/mm). The presence of a second channel in Double Channel (DC) HEMT leads to a device more sensitive towards the Single Event Transients (SET) Effect, thus, a more suitable candidate for radiation dosimeter as compared to Single Channel (SC) HEMT.

A dual gate material tunnel field effect transistor model incorporating two‐dimensional Poisson and Schrodinger wave equations

AbstractThis paper presents an accurate analytical model of surface potential and drain current for a long channel dual material gate (DMG) tunneling field‐effect transistor (TFET) with the addition of nonlinear inversion charge developed at the channel/drain interface region, ambipolar characteristic, and quantum confinement. The model includes the effect of dual metal gate work function as it controls the threshold voltage without considering a fully depleted undoped channel region. The current model includes the effect of charge accumulation at the interface of two gates and an appropriate mathematical expression of nonlinear inversion charge developed at the interface of two gates has been derived from the two‐dimensional (2D) Schrodinger wave equation incorporating quantum confinement. The model is effective to capture transfer characteristics at Sub 10 nm body thickness. A high ION/IOFF ratio and less than 27 mV/decade subthreshold swing are achieved at 2 nm body thickness which is desirable for low power VLSI application. The proposed model has been compared and calculated by Sentaurus TCAD with fair accuracy and a good resemblance, including ambipolar characteristics at sub 10 nm body thickness has been achieved.

Performance Parameter Evaluation of 7nm FinFET by Tuning Metal Work Function and High K Dielectrics

The scrambling of MOSFET below 22nm, 14nm, unwanted Short Channel Effects (SCE) like punch through, drain-induced barrier lowering (DIBL), along with huge leakage current are flowing through the device, which is not recognized for better performance. Multi-gate MOSFET generally measured as Fin-FET is the best substitute vital to stunned short channel effects. The work highlights results of the current-voltage electrical characteristics of the n-channel triple gate Fin-FET gatherings. The paper focuses on the study of geometry-based device design of Fin-FET by changing high k dielectrics materials from silicon SiO2 (3.9), Hafnium Oxide (HfO2), and metal gate work function ranging from 4.1eV to 4.5eV. The approach and simulation of 3Dimensional Fin-FET is carried to evaluate the better performance parameters of device for change in gate length by deploying different dielectrics materials. The effect on ratio of on current (ION) and off current (IOFF), threshold voltage (VTH), subthreshold slope (SS), and drain-induced barrier lowering (DIBL) is observed.

Performance Investigation of Novel Pt/Pd-SiO2 Junctionless FinFET as a High Sensitive Hydrogen Gas Sensor for Industrial Applications

In this paper, a junctionless (JL) Silicon FinFET (Fin Field effect transistor) has been designed as a hydrogen gas (H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) sensor. An analytical model has been developed to analyze the response of junctionless FinFET for detection of hydrogen gas. Palladium is used as a catalytic metal gate. The variation in the gas molecule concentration alters the pressure induced on the catalytic metal gate which changes work function of the metal gate. This variation in metal gate work function is used for detecting the presence of the hydrogen gas. Various electrical parameters for which designed gas sensor is analyzed are- surface potential, threshold voltage, drain current, transconductance, output conductance and charge concentration. The sensitivity analysis in terms of threshold voltage and drain current at different pressures is also carried out. The performance of the sensor with catalytic gate metals-palladium (Pd) and platinum (Pt) is analyzed to find which metal gate gives better response as a hydrogen gas sensor. The JL FinFET is also compared with JL Gate All Around (GAA) transistor for threshold voltage and drain current sensitivity.

Investigation on threshold voltage of p-channel GaN MOSFETs based on p-GaN/AlGaN/GaN heterostructure* *Project supported by the Key-Area Research and Development Program of Guangdong Province, China (Grant Nos. 2020B010174001 and 2020B010171002), the Ningbo Science and Technology Innovation Program 2025 (Grant No. 2019B10123), and the National Natural Science Foundation of China (Grant No. 62074122).

The threshold voltage (V th) of the p-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) is investigated via Silvaco-Atlas simulations. The main factors which influence the threshold voltage of p-channel GaN MOSFETs are barrier height Φ 1,p, polarization charge density σ b, and equivalent unite capacitance C oc. It is found that the thinner thickness of p-GaN layer and oxide layer will acquire the more negative threshold voltage V th, and threshold voltage |V th| increases with the reduction in p-GaN doping concentration and the work-function of gate metal. Meanwhile, the increase in gate dielectric relative permittivity may cause the increase in threshold voltage |V th|. Additionally, the parameter influencing output current most is the p-GaN doping concentration, and the maximum current density is 9.5 mA/mm with p-type doping concentration of 9.5 × 1016 cm−3 at V GS = –12 V and V DS = –10 V.

Design and simulation of triple metal double-gate germanium on insulator vertical tunnel field effect transistor

In this paper, a novel Triple metal double gate germanium on insulator vertical TFET is proposed and investigated by using SILVACO ATLAS TCAD tool. Gate metal work-function engineering is used to overcome the problem of low ON-current, high OFF-current, high average subthreshold swing and low ION/IOFF ratio which are present in single material double gate TFET. By modulating the values of metal gate work-functions, the performance of the device is improved. The low band-gap material and vertical tunneling concept also increase the steepness of subthreshold slope as well as ON-current of the device. Further the effects of channel length and gate to source overlap thickness on the device are also analysed to get optimum device dimensions for obtaining the improved performance results. The vertical stacking of source, channel and drain also consumes less space as compared to the conventional TFETs. So, the considerable good performance of this proposed device makes it suitable as an attractive choice for ultra-low power applications.

A review of III-V Tunnel Field Effect Transistors for future ultra low power digital/analog applications

Tunnel Field Effect Transistors (TFETs) have emerged as serious contenders for the replacement of traditional MOSFET technology for the future ultra low power Analog/Digital circuit applications because of their unique properties such as Sub-60 mV/decade subthreshold swing (SS), negligible short channel effects (SCEs) and very low off current (IOFF). This review article intensively studies the RF/Analog and DC performance of III-V materials based TFETs. This article highlights the scalability of III-V TFETs, influence of thickness and permittivity of gate dielectric, interface trap density, other geometrical dimensions, material properties and various TFET architectures on the ON and OFF state performance of III-V TFETs. This paper also point outs the impact of temperature, strain, gate metal work function, source-gate overlap and underlap, doping concentration and supply voltage scaling on the DC, RF/Analog characteristics of III-V TFETs.