Metal Gate Work Function Research Articles

Triple and quadruple metal gate work function engineering to improve the performance of junctionless double surrounding gate In0.53Ga0.47As nanotube MOSFET for the upcoming Sub 3 nm technology node

In line with Moore's Law and the International Roadmap for Devices and Systems (IDRS), shrinking MOSFET dimensions to the 3 nm technology node requires the introduction and thorough investigation of new device structures and advanced materials. The current study focuses on the implementation of Triple Metal (TM) and Quadruple Metal (QM) gate work function engineering techniques on both junctionless (JL) and inversion mode (IM) Double surrounding Gate (DSG) In0.53Ga0.47As nanotube (NT) MOSFET. The objective is to analyze the drain current (ID) characteristics for a gate length of 3 nm using Silvaco ATLAS 3D TCAD. In order to make a fair comparison between JL and IM In0.53Ga0.47As NT, the doping concentration of TM and QM JL In0.53Ga0.47As NT is tuned to achieve two specific objectives. Firstly, the goal is to produce the same ION as IM In0.53Ga0.47As NT. Secondly, the aim is to achieve the same threshold voltage (VTH) as IM In0.53Ga0.47As NT. It was discovered that the IOFF for JL devices is approximately 2.93 times smaller compared to IM devices in the TM situation, while considering matching ION and VTH. The JL devices have an IOFF that is 12.9 times smaller and an IOFF that is 102 times smaller compared to the IM device for the QM situation. This is achieved by matching the ION and VTH values. It achieves a lesser drain-induced barrier lowering (DIBL) of approximately 28.10 mV/V, a virtually perfect subthreshold slope (SS) of roughly 60mV/dec, and a larger current ratio of ION/IOFF, which is approximately 1.42 × 107.

WS2 Nanosheet-Based Ultrascaled Field-Effect Transistor for Hydrogen Gas Sensing: Addressing the Sensitivity-Downscaling Trade-Off.

In this paper, we propose an ultrascaled WS2 field-effect transistor equipped with a Pd/Pt sensitive gate for high-performance and low-power hydrogen gas sensing applications. The proposed nanosensor is simulated by self-consistently solving a quantum transport equation with electrostatics at the ballistic limit. The gas sensing principle is based on the gas-induced change in the metal gate work function. The hydrogen gas nanosensor leverages the high sensitivity of two-dimensional WS2 to its sur-rounding electrostatic environment. The computational investigation encompasses the nanosensor's behavior in terms of potential profile, charge density, current spectrum, local density of states (LDOS), transfer characteristics, and sensitivity. Additionally, the downscaling-sensitivity trade-off is analyzed by considering the impact of drain-to-source voltage and the electrostatics parameters on subthreshold performance. The simulation results indicate that the downscaling-sensitivity trade-off can be optimized through enhancements in electrostatics, such as utilizing high-k dielectrics and reducing oxide thickness, as well as applying a low drain-to-source voltage, which also contributes to improved energy efficiency. The proposed nanodevice meets the prerequisites for cutting-edge gas nanosensors, offering high sensing performance, improved scaling capability, low power consumption, and complementary metal-oxide-semiconductor compatibility, making it a compelling candidate for the next generation of ultrascaled FET-based gas nanosensors.

Enhanced breakdown voltage for p-GaN gate AlGaN/GaN HEMT on AlN/Si with triple trenches: A simulation study

This study presents an analysis of an AlGaN/GaN high-electron-mobility transistor (HEMT) with a triple-trench structure (TT-HEMT) for the enhancement of breakdown voltage, which is often limited by the high electric field near the gate edge. Using COMSOL Multiphysics, simulations were run, with trenches made of gallium nitride (GaN) constructed between the GaN and aluminum nitride (AlN) nucleation layers. Each trench was positioned directly beneath the source, gate, and drain contacts. Under the metal gate, a p-type doped GaN cap is added to produce an enhancement mode device, which is more desirable in high-power applications. The results indicate that the effective dispersion of the electric field distribution enhances the breakdown voltage of the device by 70 % in comparison to a conventional HEMT. Additionally, the impact of various design parameters, such as the p-GaN doping concentration and the metal gate work function on the electrical performance, was also investigated. Overall, the proposed device structure exhibits superior electrical properties for high-power applications.

Metal gate work function engineering for nano-scaled trigate FinFET

Metal gate work function engineering for nano-scaled trigate FinFET

Study on trap sensitivity for single material gate and double material gate nano-ribbon FETs

In this work, the trap sensitivity of single material gate (SMG) and dual material gate (DMG) nano ribbon FETs (NRFETs) are reported using TCAD Sentaurus Device simulator. The trap sensitivity is extracted for Gaussian trap distribution of both acceptor and donor type traps. We have reported the trap sensitivity for the variation in trap concentration, energy peak position, work function of metal gate, and temperature for both the NRFETs. It is realized that trap sensitivity is greater and lesser than 100% for acceptor type trap in SMG and DMG NRFETs, respectively, whereas, such sensitivity is 147% and 123% for donor type trap concentration, respectively. Temperature also shows a significant variation in trap sensitivity for both the NRFETs. The increase in work function leads to the reduction in trap sensitivity for both NRFETs in existence of acceptor and donor trap charges. The maximum sensitivity in trap are 400% and 275% for SMG and DMG NRFETs, respectively, in presence of donor trap concentration. Moreover, the trap sensitivity is very insignificant at high gate bias for donor type trap concentration with wide variation in parameters.

Sensitivity enhancement using triple metal gate work function engineering of junctionless cylindrical gate all around SiNW MOSFET based biosensor for neutral biomolecule species detection for upcoming sub 14 nm technology node

In the present work Dielectric Modulation (DM) technique along with Triple Metal (TM) gate engineering has been used for the junctionless (JL) cylindrical gate all around (CGAA) Si nanowire (NW) MOSFET based biosensor for label free electrical detection of neutral biomolecules species like Uricase, Streptavidin, Protein, Biotin, ChOx (choline oxidase), and APTES etc. For this device, the Drift Diffusion approach has been used along with self-consistent solution of Schrodinger’s equation with Poisson’s equation. For the biomolecule immobilization, a nanogap cavity region is formed in the JL SiNW MOSFET by etching gate oxide layer above the SiO2 interfacial layer. The change in the drain current (ID), threshold voltage (Vth), off-current sensitivity (SIoff), threshold voltage sensitivity (SVth) and Ion/Ioff current ratio of the device have been considered as the sensing parameters for detection of biomolecules under dry environment condition. In present work a new sensing metric of sensing of biomolecules – DIBL has been added which has never been reported in literature. In this work for JL SiNW, sensitivity metrics like smaller DIBL ∼50.47 mV/V, higher SIoff9.33×105, higher SVth28.72, nearly ideal subthreshold slope (SS) ∼60 mV/dec, and higher Ion/Ioff current ratio ∼9.01 × 1012 have been obtained in comparison to available literature results.

Leaky-integrate-fire neuron based on vertically extended drain Si[formula omitted]Ge[formula omitted] source TFET: Ultra-energy-efficient and high speed design

This article investigates the performance of a vertically extended drain double gate Si1−x Gex source tunnel field effect transistor (VD-DG-Si1−x Gex S-TFET) as a leaky integrate-and-fire (LIF) neuron. The proposed VD-DG-Si1−x Gex S-TFET structure has been designed and optimized by deploying the commercially available Silvaco TCAD. The LIF neuron using VD-DG-Si1−x Gex S-TFET requires a low spiking threshold voltage (i.e. 0.20 V) which is 5x, 3x, 5x, 1.3x, 1.55x, 7.5x, and 1.44x times less in comparison to MOSFET, Bulk FinFET, phase change device, SOI MOSFET, DG-JLFET, silicon nanowire, and DL-TFET silicon neuron. The proposed device based neuron demonstrates the least spiking energy (177 ZJ) reported to date which is 18192 times less as compared to BTBT based PDSOI MOSFET neuron. The threshold value of current is achieved at 0.20 V drain voltage which is 15x, 14x, 10x, and 1.5x less as compared to FinFET, PD-SOI MOSFET, LBIMOS, and DL-TFET, respectively. Moreover, the effects of gate metal work function, germanium mole fraction, and temperature on the spike current variations have also been investigated. Here, impact ionization is a key method for generating a neuron spike due to holes accumulated in the potential well of VD-DG-Si1−xGex S-TFET. In addition, a LIF neuron based on VD-DG-Si0.5Ge0.5 S-TFET device exhibits a 9 THz spiking frequency which is approximately 12 times higher than real nerves present in the human body. This work shows a remarkable reduction in the power consumption and the proposed device neuron is a potential start-up solution for a large scale spiking neural networks (SNN) implementation because of its better performance and compact circuitry.

Analysis and modeling of the influence of gate leakage current on threshold voltage and subthreshold swing in p-GaN gate AlGaN/GaN high electron mobility transistors

In this paper, the p-GaN gate AlGaN/GaN high electron mobility transistors (HEMTs) with varying combinations of gate metal work function and gate geometry are fabricated and investigate the influence of gate leakage current (IGS) on the threshold voltage (VTH) and subthreshold swing (SS). The unique dependence of VTH and SS on gate geometry for different metals is observed, which is different from traditional field-effect transistors. A novel hybrid physics model, consisting of the traditional capacitance divider model and hole injection model, is proposed to explain this phenomenon, and the results exhibit an excellent agreement with the experimental data. The holes traverse the gate/p-GaN Schottky barrier by thermal emission or tunneling and inject into the p-GaN layer, generating the IGS. Expanding upon the traditional capacitance divider model, a portion of the injected holes accumulate at the p-GaN/AlGaN interface and induce the corresponding electrons at the AlGaN/GaN heterojunction, which promotes channel conduction. Hence, the transfer curves display the correlation between IGS and VTH as well as SS. The results show that high IGS can alleviate the instability of VTH caused by the lithographic overlay error, and simultaneously optimize SS. This work offers a novel perspective for examining the turn-on mechanism of p-GaN HEMTs, thereby contributing to device design.

Dielectrically-Modulated GANFET Biosensor for Label-Free Detection of DNA and Avian Influenza Virus: Proposal and Modeling

This paper introduces a novel device called the Gate All Around Engineered Gallium Nitride Field Effect Transistor (GAAE-GANFET), designed specifically for label-free biosensing applications. This innovative gate-all-around engineering in GANFET integrates various device engineering techniques, such as channel engineering, gate engineering, and oxide engineering, to enhance biosensing performance. The channel engineering techniques refer to the use of a gallium nitride channel with a step-graded doping profile, divided into three distinct regions. In contrast, the gate engineering technique refers to the cylindrical split-gate-underlap architecture. The oxide engineering technique involves stacking Al2O3 and HfO2. Moreover, this biosensor incorporates two-sided gate underlap cavities that facilitate the immobilization of biomolecules. These open cavities not only provide structural stability but also simplify the fabrication process to a significant extent. The viability of this biosensor as a label-free biosensor has been evaluated using an antigen and an antibody from the Avian Influenza virus and DNA as the target biomolecules. The proposed analytical model and TCAD simulation results are in excellent agreement, demonstrating the reliability of the proposed device. Additionally, the biosensor’s sensitivity, which depends on cavity length, doping concentration, gate metal work function, and temperature variation, has been thoroughly explored. The gate-all-around structure, along with the integration of tri-step graded doping, GaN as the channel material, gate oxide stacking, and dual open cavity structure in the proposed biosensor, leads to significantly improved biosensing capabilities.

Investigation of dual work function metal (DWFM) gate stacks with ALD TaAlN and TaAlC for multi threshold voltages (VTHs) engineering in MOS device integration

This study investigates methods to modulate the effective work function (EWF) and control the multiple threshold voltages (VTHs) of metal-oxide-semiconductor (MOS) devices by applying metal electrodes with different work function materials (WFMs), including a single layer of n-type (TaAlC) and p-type (TaAlN) as well as their stacked structures, through atomic layer deposition (ALD). Dual-Work-Function-Metal (DWFM) gate is a crucial aspect of confirming the feasibility of metal gate stacks in MOS devices for a complementary metal-oxide-semiconductor (CMOS) integration scheme. The gate stack structure of p-Si/IL (Inter layer)/HfO2/DWFM (p/n-type compatible metal stack)/W exhibits good adhesion and even chemical composition distribution, as evidenced by transmission electron microscope (TEM) and energy dispersive spectrometer (EDS) analysis. By fabricating MOS capacitors using this WFM structure and extracting EWF from the measured capacitance-voltage (C–V) characteristics, EWF values of 4.62 eV and 4.99 eV were identified both before and after annealing using forming gas, indicating pWFM-like properties. These properties are attributed to the strengthened Al–O bonds and reduced CO peaks seen in x-ray photoelectron spectroscopy (XPS) analysis. The use of different Ta precursor from Tris(diethylamido)(tert-butylimido)tantalum(V) (TBTDET) as well as TaCl5 resulted in the increase of the EWF following the unique p-WFM like feature. As candidates for WFM electrode in metal-oxide-semiconductor field effect transistor (MOSFET) with the DWFMs (n/p stacks) were evaluated, resulting in a VTH of 0.84 V that places in the middle of the VTH shift range from 0.6 V (nWFM) to 1.16 V (pWFM), approximately. The DWFMs allow for modulation of the EWF, which in turn reduces ambiguity in addressing replacement metal gate (RMG) challenges and opens up new avenues for achieving multi-VTH solutions in CMOS integration schemes.

Mole Fraction and Device Reliability Analysis of Vertical-Tunneling-Attributed Dual-Material Double-Gate Heterojunction-TFET with Si0.7Ge0.3 Source Region at Device and Circuit Level

This paper puts forward a new vertical-tunneling-attributed dual-material double-gate heterojunction-TFET (VTDMDG-HTFET). The device structure of VTDMDG-HTFET includes Si[Formula: see text]Ge[Formula: see text] material for the designing of source region. The mechanism of vertical tunneling in VTDMDG-HTFET provides superior electric field at tunneling interface and leads to improved transfer characteristics. VTDMDG-HTFET also includes metal gate work-function engineering approach to facilitate high ON-current and small OFF-current. Application of high-[Formula: see text] dielectric material HfO2 in the form of gate oxide enhances the capacitive-coupling at channel-source interface. Moreover, the work includes the comparison of proposed VTDMDG-HTFET with the conventional vertical-tunneling based dual-material double-gate-TFET (VTDMDG-TFET). It has been observed from the simulation results that SiGe source-based VTDMDG-HTFET offers better DC characteristics in terms of superior ON-current, smaller OFF-current, steeper subthreshold-slope, lower threshold voltage, higher transconductance along with smaller drain-induced barrier-lowering (DIBL) effects as compared to its counterpart silicon-source-based VTDMDG-TFET. In this work, reliability of VTDMDG-HTFET has also been examined and compared with VTDMDG-TFET in terms of temperature sensitivity and effect of different interface trap charges. The device simulation and investigations have been carried out using technology computer aided design (TCAD) tool. Moreover, device circuit mixed-mode simulation analysis is carried out for conventional and proposed device based resistive load inverters. A comparison is performed between both the inverters in terms of prorogation delay and switching threshold voltages. Further, the mixed mode simulation analysis is also performed for the proposed device based inverter under the influence of different interface trap charges (ITCs). Study shows that reliability performance of the proposed device is better as compared to its counterpart conventional device. Hence, vertical tunneling and SiGe source-based VTDMDG-HTFET can be a better choice for various applications such as analog/RF, analog and digital electronic circuits, energy harvesting, gas-sensing and memory devices.

A proof of concept for reliability aware analysis of junctionless negative capacitance FinFET-based hydrogen sensor

This work demonstrates the reliability-aware analysis of the Junctionless negative capacitance (NC) FinFET employed as a hydrogen (H2) gas sensor. Gate stacking of the ferroelectric (FE) layer induces internal voltage amplification owing to the NC property, thus, improving the sensitivity of the baseline junctionless FinFET. A well-calibrated TCAD model is used to investigate the sensing characteristics of the proposed FinFET-based H2 sensor by employing the palladium (Pd) metallic gate as a sensing element. The mechanism involves the transduction of H2 gas molecules over the metal gate; due to the diffusion process, some atomic hydrogen diffuses into the metal. The H2 gas absorption at the metal surface causes a dipole layer formation at the gate and oxide interface, which changes the metal gate work function. As a result, this change in the work function can be used as a sensing parameter of the proposed gas sensor. Further, the threshold voltage and other electrical characteristics, such as output conductance, transconductance, and drain current are examined for sensitivity analysis for both NC and without NC JL FinFET at different pressure ranges, keeping the temperature constant (i.e. 300 K). The device variation, i.e. Fin thickness, Fin height, doping and thickness of HfO2 ferroelectric layer, etc, on sensor sensitivity has been evaluated through extensive simulation. This paper also presents a detailed investigation of the sensor’s reliability in terms of work function variation, random dopant fluctuation, trap charges, and device aging, i.e. end of a lifetime. At last, the acquired results are compared with earlier reported data, which justifies the profound significance of the proposed junctionless negative capacitance FinFET-based H2 gas sensor.

Effects of metal work function and gate-oxide dielectric on super high frequency performance of a non-align junction DG-MOSFET based inverter in the sub-100 nm regime: a TCAD simulation analysis

ABSTRACT This paper presents simulation analysis of an inverter made from non-aligned double gate field effect transistors (NADGFETs) in Sub-100 nm regime. The inverter consists of n-channel NADGFET and p-channel NADGFET device with a channel length of 40 nm and 50% non-alignment between gate and source/drain. The response of the inverter was tested by a combination of gate dielectric constant (k) and metal work function (ϕ). Three gate dielectrics namely, SiO2 (k = 3.9), Si3N4 (k = 7.2), HfO2 (k = 24), and three metal work function namely tungsten (ϕ = 4.5 eV), molybdenum (ϕ = 4.75 eV), gold (ϕ = 5 eV), were considered in the NADGFET inverter. This paper defines a kϕ index as characterising parameter to explore the best response from inverter configuration with minimum propagation delay, and minimum power consumption at super-high frequency. The paper proposes to analyse the NADGNFET device, in term of ION current, ION/IOFF ratio, cut-off frequency, and gate delay. And observes that low k material with moderate metal work function gives best response. The work then simulates the inverter and group the results into voltage transfer curve (VTC), transient response, and power dissipation category. The result shows that when inverter was subjected to high frequency, all the kϕ combination responds good, however when the inverter was subjected to super-high frequency, the low value of kϕ combination performs well. Thus, the result concludes that SiO2-M2 combination will be best selection to get minimum propagation delay and dynamic power dissipation by the inverter. The test strategy presented in this paper on the basis of kϕ index can serve as benchmark to test inverter device at super-high frequency.

Performance analysis of metal gate engineered junctionless nanosheet fet with a ft/fmax of 224/342ghz for beyond 5g (b5g) applications

This manuscript for the first time investigates the effect of Dual Metal on Gate Junctionless Nanosheet FET (DMG-JL-NSFET) for analog/RF applications. The entire analysis is performed for gate length (Lg) = 16 nm at 10μA/μm to focus the weak/moderate inversion region of operation. The results show a whooping amount of reduction in terms of output conductance (gds) (∼88.8%) due to the screening effect thereby enhancing the intrinsic gain (AV) (∼28.97%) of the DMG-JL-NSFET as compared to SMG-JL-NSFET. It is also found that the cut-off frequency (fT) and maximum oscillation frequency (fMAX) are increased by an amount of ∼11.82% and ∼2.91% respectively for DMG-JL-NSFET. Furthermore, it is elucidated that increasing the metal gate work function work difference (ΔW = φms-φmd) reduces the analog/RF performance of the DMG-JL-NSFET. The analysis revealed that increasing the ΔW from 0.3eV to 0.7eV deteriorates AV, fT, fMAX by an amount of ∼17.35%, ∼19.21%, and ∼37.57% respectively. Moreover, the implementation of HfO2 as high-k gate dielectric as a replacement for SiO2 degrades the analog/RF efficiency of DMG-JL-NSFET. Moreover, the DMG-JL-NSFET has provided a greater fT (∼224 GHz)/fMAX (∼342 GHz) indicating a promising candidature for future beyond 5G (B5G) applications.

Trap sensitivity of splitted source Z Shape horizontal pocket and hetero stack TFETs: a simulation study

This paper reports the trap sensitivity analysis of split source horizontal pocket Z shape tunnel field effect transistor (ZHP-TFET) and hetero stack TFET (HS-TFET) using technology computer aided design (TCAD) simulator. The sensitivity analysis elaborates the significance of ideal trap charges at the interface of oxide and semiconductor material for both acceptor and donor like traps. The trap sensitivity analysis is highlighted for variation in trap-concentrations, temperature, gate-metal work function, and peak energy position, for both the TFETs. Furthermore, we have implemented digital inverter on taking into account the interface trap charges effect. Result reveals that tarp sensitivity on various electrical parameter of HS-TFET is significantly higher than ZHP-TFET. It is seen that ZHP-TFET provides sensitivity around 11 and 33 under acceptor and donor impurities, respectively, whereas, for HS-TFET sensitivity is around 22 and 60 for acceptor and donor impurities, respectively, for wide variation in trap concentration. The voltage transfer characteristic and voltage gain of digital inverter are improved by observable amount in ZHP-TFET than HS-TFET for both donor and acceptor like trap. The noise margin of ZHP-TFET based resistive inverter comes 0.75 V, 0.73 V, and 0.77 V, while in case of HS-TFET these value noted as 0.32 V, 0.13 V and 0.37 V under consideration for no trap, acceptor trap, and donor trap, respectively.

Impact of Gate Metal Work-function for On-to-off Current Ratio and Threshold Voltage in Junctionless Gate-All-Around (GAA) MOSFET Stacked with SiO2 and High-k Dielectric

The relationship among the on-to-off current ratio, threshold voltage, and the gate metal work-function is investigated for a junctionless (JL) Gate-All-Around (GAA) MOSFET with a gate oxide film in which SiO2 and a high-k dielectric material are stacked. The JL structure works in the accumulation state, and the threshold voltage is defined as the gate voltage when the minimum potential in the channel becomes Fermi potential. The on-to-off current ratio Ion/Ioff is obtained by obtaining on-current Ion at the threshold voltage and off-current Ioff at the gate voltage of 0 V. As a result, if the channel doping concentration and silicon radius are increased to reduce the channel resistance, the on-to-off current ratio decreases along with the threshold voltage, but this problem can be solved through the increasing of the gate metal workfunction. In addition, even when the relative permittivity of the high-k dielectric is increased from 3.9 to 20, the gate metal work-function to maintain any on-to-off current ratio and threshold voltage is very slightly changed. Therefore it will be possible to improve the controllability of the gate by increasing the permittivity of the high-k dielectric without change in the work-function. The reduction of the channel resistance of the JL GAA MOSFET is possible with the stacked gate oxide while maintaining a reasonable on-to-off current ratio and threshold voltage by adjusting the gate metal work-function

Investigation on impact of AlxGa1-xN and InGaN back barriers and source-drain spacing on the DC/RF performance of Fe-doped recessed T-gated AlN/GaN HEMT on SiC wafer for future RF power applications

The work function (φm) of gate metal is crucial to electrical characteristics in standard GaN-based high electron mobility transistors (HEMTs). In this simulation report, RF & DC performance of recessed T-gated Fe-doped AlN/GaN HEMT device with AlxGa1-xN back barrier (BB) and InGaN BB is explored by varying gate metal work functions which is a flexible approach to obtain wide modulation range of threshold voltage (Vth) with a positive shift. The simulations are carried out at an applied drain voltage of 1.4 V. As Al-content of AlxGa1-xN BB layer has an impact on surface roughness with GaN channel and effective mobility of electrons in the two-dimensional electron gas (2DEG), this work includes tuning the aluminum mole fraction. In comparison, the proposed device with Al0.15Ga0.85N BB layer exhibits high GM of 381.4 mS/mm with φm = 5.25 eV, highest ID of 0.702 A/mm with φm = 4.5 eV, and high fT/fmax of 173.1/247.4 GHz with φm = 5.25 eV which can be ascribed to enhanced mobility and carrier confinement in the quantum well due to integration of BB, presence of Fe-doping in the buffer in conjunction with recessed T-gate approach. Hence, optimized performance is achieved with Al0.15Ga0.85N BB layer at φm = 4.5 eV. In addition, we investigated the effect of scaling gate-to-source spacing (LGS) with constant gate-to-drain spacing (LGD) and vice-versa, on the device performance. The device with Al0.15Ga0.85N BB exhibited supreme performance at LGS = 300 nm with LGD = 800 nm, due to enhanced electric field component along the channel as a result of downscaling lateral device dimensions. No wonder, this device can be considered as most promising for future military, defence, and RF power applications.

Vertical GaN/InGaN/GaN heterostructure tunnel field-effect transistor: DC and analog/RF performance

This work reports an [Formula: see text]-type GaN/InGaN/GaN heterostructure vertical double-gate tunnel field-effect transistor (VTFET) using exhaustive calibrated simulation for the first time. Investigation has been done for the proposed structure by including a polarization layer of InGaN near the source-channel junction. From the analysis, it has been observed that after the introduction of polarization layer near the source-channel interface, drain current increases due to the increase in charge concentration (2DEG) near the interface due to inter-band tunneling. Value of 2DEG concentration achieved post introducing the polarization layer is [Formula: see text] [Formula: see text]. The reported structure is optimized using parametric sweep optimization technique. Here, a detailed dc and analog/RF performance estimation has been done for the structure with heterostructure. In-depth sensitivity analysis has been done for the structure with the polarization layer. It is reported that the structure with HfO2 as the dielectric material with [Formula: see text] of 2 nm and with gate metal work function of 5.8 eV gives the optimum performance at 300 K. Further, it demonstrates high cutoff frequency ([Formula: see text] and gain bandwidth product (GBW) as 1000 GHz and 300 GHz, respectively. Hence, the reported structure is a better alternative for high-power steep switching analog and RF applications.

GeSn based heterojunction double-gate tripple metal layer vertical TFET with enhanced DC and Analog/RF performance

In this article, low-bandgap material GeSn and high bandgap Si material heterojunction (GeSn/Si) based double gate triple metal layer Vertical TFET is designed and analyzed by ATLAS Silvaco TCAD simulation tool. Higher ON-state current is obtained by this device owing to (i) the usage of novel low band-gap material i.e., GeSn and (ii) Vertical tunneling as the gate overlaps the source region. The incorporation of GeSn material not only enhances the ON-state current but also improves the SS, albeit trading off the OFF-state current and ambipolar current of the device. To control the ambipolar current and OFF-state current, variation in the gate to drain overlap and auxiliary gate metal work function has been done. The impact of the gate to drain overlap and auxiliary gate workfunction variation has been studied for various electrical parameters. Further through extensive simulation analysis, optimized dimensions have been obtained. An enormously high ION/IOFF ratio of the order of 1.6 × 1012, steepest point, and average subthreshold swing of 7.5 mV/dec and 12.3 mV/dec respectively has been achieved through this proposed device. In addition to this, comparison of the proposed device with other novel TFET devices reported in literature has been done. From the comparison, it has been concluded that better results are obtained by the proposed device in terms of ION, IAMB, ION/IOFF ratio, SSavg, and gm. Therefore, this novel proposed device can be used as a promising device for various small power applications. Further, this device not only provides improved DC and Analog/RF electrical parameters but also provides small footprint due to vertically aligned architecture.

Exploring the performance of palladium gated – SiGe channel – Polarity controllable–FET for hydrogen gas monitoring applications

In the current work, a silicon-germanium (SiGe) channel-based Polarity Controllable FET (SiGe-PC-FET) has been investigated as a potential candidate in hydrogen gas sensing applications. The change in pressure of hydrogen gas molecules alters the work-function of Palladium gate metal which results in shift in electrical characteristics of the device. Further, the change in temperature along with mole-fraction of Ge in SiGe channel also plays a crucial role in determining the performance of gas sensor and thus, an exhaustive analysis in terms of various characteristics such as energy-band, surface potential, IDS – VCG and IDS – VDS has been carried out for a wide temperature range. Furthermore, the sensitivity analysis has been carried out in terms of drain-current, ION/OFF, transconductance and drain-conductance parameters at different pressures and temperatures. It has been demonstrated that even at elevated temperatures, the proposed gas sensor continues to offer improved sensitivity for a wide range of pressure values.