Wordlength Constraints Research Articles

An Examination of and a Commentary on the Increased Length of Published Research Papers

ABSTRACTThe page lengths of the articles in the top accounting journals have been steadily increasing over the past two decades. The increase is about 42 percent using the average page length, and 45 percent using the median page length.These length increases are understated because the more recent articles now include online supplementary materials that are not counted as published pages. The number of authors per article has also increased over the past two decades from 2.1 authors to an average of 2.8 authors per article. To reduce the level of editors', reviewers', and our colleagues in the academe's fatigue, journal editors should consider word length constraints. Also, making our research more appealing to accounting professionals, policymakers, and the public is another incentive for journal editors to consider word length constraints.Data Availability: The data are available from the author on request.JEL Classifications: M21; M40.

Static quantised radix-2 fast Fourier transform (FFT)/inverse FFT processor for constraints analysis

This research work focuses on the design of a high-resolution fast Fourier transform (FFT)/inverse FFT (IFFT) processors for constraints analysis purpose. Amongst the major setbacks associated with such high-resolution FFT processors are the high-power consumption resulting from the structural complexity and computational inefficiency of floating-point calculations. As such, a parallel pipelined architecture was proposed to statically scale the resolution of the processor to suite adequate trade-off constraints. The quantisation was applied to provide an approximation to address the finite word-length constraints of digital signal processing. An optimum operating mode was proposed, based on the signal-to-quantisation-noise ratio (SQNR) as well as the statistical theory of quantisation, to minimise the trade-off issues associated with selecting the most application-efficient floating-point processing capability in contrast to their resolution quality.

A 100-MHz 2-D discrete cosine transform core processor

A 100-MHz two-dimensional discrete cosine transform (DCT) core processor applicable to the real-time processing of HDTV signals is described. An excellent architecture utilizing a fast DCT algorithm and multiplier accumulators based on distributed arithmetic have contributed to reducing the hardware amount and to enhancing the speed performance. A layout scheme with a column-interleaved memory and a new ROM circuit are introduced for the efficient implementation of memory-based signal processing circuits. Furthermore, mean values of errors generated in the core were minimized to enhance the computational accuracy with the word-length constraints. Consequently, it features the fastest operating speed and the smallest area with sufficient accuracy to satisfy the specifications in CCITT recommendation H.261. The core integrates about 102 K transistors and occupies 21 mm/sup 2/ using 0.8- mu m double-metal CMOS technology. >

Large integer multiplication on hypercubes

Previous work has reported on the use of polynomial transforms to compute exact convolution and to perform multiplication of large integers on a massively parallel processor. We now present results of an improved technique, using the Fermat Number Transform. When the Fermat Number Transform was first proposed, word-length constraints limited its effectiveness. Despite the development of multidimensional techniques to extend the length of the FNT, the relatively small word length of existing machines made the transform of little more than academic interest. The emergence of new computer architectures, however, has made the Fermat Number Transform more attractive. On machines like the Connection Machine, for example, we may implement the Fermat Number Transform without regard to word-length considerations. We present a convolution algorithm on a massively parallel processor, based on the Fermat Number Transform. We present some examples of the trade-offs between modulus, interprocessor communication steps, and input size. We then discuss the application of this algorithm in the multiplication of large integers and report performance results on a Connection Machine. Our results show multiplication times ranging from about 50 ms for 2-kbit integers to 2 s for 8-Mbit integers, an improvement of about five times over previous work.

Efficient number theoretic transforms for convolutions using ROM arrays

Hardware realisations are proposed of number theoretic transforms (NTTs) that are based on the transformation of their fundamental relationships into recursive filter forms with single integer poles. Furthermore, use is made of read-only memory (ROM) to effect the multiplications by the root of unity, α. Suitable NTTs are then suggested for the fast computation of cyclic convolutions using multidimensional and multi-modular techniques. The required ROM size in the proposed realisations is small and the control of data flow is simple and straightforward. This new class of number theoretic transforms can relax considerably the normal sequence length and wordlength constraints for the NTT.

Adaptive filtering with finite wordlength constraints

Adaptive filtering with finite wordlength constraints

Selecting state variables to minimize eigenvalue sensitivity of multivariable systems

It often happens that linear, time invariant, multivariable systems must be simulated or synthesized using digital and analog computers. The simulation may require accurate reproduction of the simulated system, and the synthesis may demand faithful representation of a mathematical model. Because of the degradation introduced by such factors as the finite wordlength constraints of digital computers and the temperature variation of amplifier gains in analog computers, the computer realization will differ from its original model. In this paper a simple method is presented for minimizing the deviation in the eigenvalues of the computer realization when all elements of the system matrix are subject to simultaneous variations. This procedure involves the selection of a suitable set of state variables, the choice depending simply on the location of the system eigenvalues. When the system is realized using the state vector obtained by this method, greater component variations and shorter computer wordlengths can be tolerated before stability is sacrified and satisfactory behavior is compromised. As a result, utilization of the algorithm discussed in this paper can result either in relaxation of computer tolerances, and hence reducing the cost of realization, or in more faithful reproduction of the original system.